[llvm] [AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (PR #114232)

[Jay Foad via llvm-commits]

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@@ -230,13 +230,6 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
     return AddrReg.getReg(0);
   }
 
-  void assignValueToReg(Register ValVReg, Register PhysReg,
-                        const CCValAssign &VA) override {
-    MIB.addUse(PhysReg, RegState::Implicit);
-    Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
-    MIRBuilder.buildCopy(PhysReg, ExtReg);
-  }
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jayfoad wrote:

This is overriding the base class implementation `AMDGPUOutgoingValueHandler::assignValueToReg` and the only difference is that it _removes_ the readfirstlane stuff.

https://github.com/llvm/llvm-project/pull/114232