[llvm] [CodeGen] Avoid sinking vector comparisons during CodeGenPrepare (PR #113158)

[David Sherwood via llvm-commits]

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@@ -2389,7 +2389,7 @@ class TargetLoweringBase {
                                                EVT VT) const {
     // If a target has multiple condition registers, then it likely has logical
     // operations on those registers.
-    if (hasMultipleConditionRegisters())
+    if (hasMultiplePredicateRegisters(VT))
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david-arm wrote:

Ah yes, I think you might be right! I'd just assumed (probably wrongly) that VT was the result type. I've fixed this now.

https://github.com/llvm/llvm-project/pull/113158