[llvm] [CodeGen] Add preliminary plumbing for `samesign` flag (PR #112354)
Antonio Frighetto via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 30 07:03:59 PDT 2024
https://github.com/antoniofrighetto updated https://github.com/llvm/llvm-project/pull/112354
>From 7c49142ae3cf1d7de22777354768547cb7625f08 Mon Sep 17 00:00:00 2001
From: Antonio Frighetto <me at antoniofrighetto.com>
Date: Tue, 15 Oct 2024 15:08:25 +0200
Subject: [PATCH] [CodeGen] Add preliminary plumbing for `samesign` flag
Extend recently-added poison-generating IR flag to codegen as well.
---
.../CodeGen/GlobalISel/GenericMachineInstrs.h | 2 +-
.../CodeGen/GlobalISel/MachineIRBuilder.h | 3 +-
llvm/include/llvm/CodeGen/MachineInstr.h | 1 +
llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 8 +++-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 8 ++--
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 5 ++-
llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MILexer.h | 1 +
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 5 ++-
llvm/lib/CodeGen/MIRPrinter.cpp | 2 +
llvm/lib/CodeGen/MachineInstr.cpp | 8 ++++
.../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 3 ++
.../SelectionDAG/SelectionDAGBuilder.cpp | 4 ++
.../SelectionDAG/SelectionDAGDumper.cpp | 3 ++
.../GlobalISel/irtranslator-icmp-samesign.ll | 33 +++++++++++++++
llvm/test/CodeGen/MIR/X86/icmp-samesign.mir | 40 +++++++++++++++++++
16 files changed, 116 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-icmp-samesign.ll
create mode 100644 llvm/test/CodeGen/MIR/X86/icmp-samesign.mir
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index b6309a9ea0ec78..cd7ebcf54c9e1e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -28,7 +28,7 @@ namespace llvm {
class GenericMachineInstr : public MachineInstr {
constexpr static unsigned PoisonFlags = NoUWrap | NoSWrap | NoUSWrap |
IsExact | Disjoint | NonNeg |
- FmNoNans | FmNoInfs;
+ FmNoNans | FmNoInfs | SameSign;
public:
GenericMachineInstr() = delete;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index ab3025e4923cd0..c7730cf2cfef9b 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1255,7 +1255,8 @@ class MachineIRBuilder {
///
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
- const SrcOp &Op0, const SrcOp &Op1);
+ const SrcOp &Op0, const SrcOp &Op1,
+ std::optional<unsigned> Flags = std::nullopt);
/// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
///
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 36051732474634..f064bacf15902d 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -119,6 +119,7 @@ class MachineInstr
Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
NoUSWrap = 1 << 20, // Instruction supports geps
// no unsigned signed wrap.
+ SameSign = 1 << 21, // Compare instruction has same sign.
};
private:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 26488413fe5826..e76c6f8bf61df3 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -410,12 +410,14 @@ struct SDNodeFlags {
NoFPExcept = 1 << 12,
// Instructions with attached 'unpredictable' metadata on IR level.
Unpredictable = 1 << 13,
+ // Compare instructions which may carry the samesign flag.
+ SameSign = 1 << 14,
// NOTE: Please update LargestValue in LLVM_DECLARE_ENUM_AS_BITMASK below
// the class definition when adding new flags.
PoisonGeneratingFlags = NoUnsignedWrap | NoSignedWrap | Exact | Disjoint |
- NonNeg | NoNaNs | NoInfs,
+ NonNeg | NoNaNs | NoInfs | SameSign,
};
/// Default constructor turns off all optimization flags.
@@ -437,6 +439,7 @@ struct SDNodeFlags {
void setNoSignedWrap(bool b) { setFlag<NoSignedWrap>(b); }
void setExact(bool b) { setFlag<Exact>(b); }
void setDisjoint(bool b) { setFlag<Disjoint>(b); }
+ void setSameSign(bool b) { setFlag<SameSign>(b); }
void setNonNeg(bool b) { setFlag<NonNeg>(b); }
void setNoNaNs(bool b) { setFlag<NoNaNs>(b); }
void setNoInfs(bool b) { setFlag<NoInfs>(b); }
@@ -453,6 +456,7 @@ struct SDNodeFlags {
bool hasNoSignedWrap() const { return Flags & NoSignedWrap; }
bool hasExact() const { return Flags & Exact; }
bool hasDisjoint() const { return Flags & Disjoint; }
+ bool hasSameSign() const { return Flags & SameSign; }
bool hasNonNeg() const { return Flags & NonNeg; }
bool hasNoNaNs() const { return Flags & NoNaNs; }
bool hasNoInfs() const { return Flags & NoInfs; }
@@ -474,7 +478,7 @@ struct SDNodeFlags {
};
LLVM_DECLARE_ENUM_AS_BITMASK(decltype(SDNodeFlags::None),
- SDNodeFlags::Unpredictable);
+ SDNodeFlags::SameSign);
/// Represents one node in the SelectionDAG.
///
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 5381dce58f9e65..9a281bac912f24 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -340,8 +340,11 @@ bool IRTranslator::translateCompare(const User &U,
Register Op1 = getOrCreateVReg(*U.getOperand(1));
Register Res = getOrCreateVReg(U);
CmpInst::Predicate Pred = CI->getPredicate();
+ uint32_t Flags = 0;
+ if (CI)
+ Flags = MachineInstr::copyFlagsFromInstruction(*CI);
if (CmpInst::isIntPredicate(Pred))
- MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
+ MIRBuilder.buildICmp(Pred, Res, Op0, Op1, Flags);
else if (Pred == CmpInst::FCMP_FALSE)
MIRBuilder.buildCopy(
Res, getOrCreateVReg(*Constant::getNullValue(U.getType())));
@@ -349,9 +352,6 @@ bool IRTranslator::translateCompare(const User &U,
MIRBuilder.buildCopy(
Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType())));
else {
- uint32_t Flags = 0;
- if (CI)
- Flags = MachineInstr::copyFlagsFromInstruction(*CI);
MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 59f2fc633f5de7..15b9164247846c 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -898,8 +898,9 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op,
MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
const DstOp &Res,
const SrcOp &Op0,
- const SrcOp &Op1) {
- return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
+ const SrcOp &Op1,
+ std::optional<unsigned> Flags) {
+ return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}, Flags);
}
MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 5a3806ce57335a..1c450b05f49e93 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -216,6 +216,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("exact", MIToken::kw_exact)
.Case("nneg", MIToken::kw_nneg)
.Case("disjoint", MIToken::kw_disjoint)
+ .Case("samesign", MIToken::kw_samesign)
.Case("nofpexcept", MIToken::kw_nofpexcept)
.Case("unpredictable", MIToken::kw_unpredictable)
.Case("debug-location", MIToken::kw_debug_location)
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 3931da3eaae1d3..d7cd06759cfbb8 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -77,6 +77,7 @@ struct MIToken {
kw_unpredictable,
kw_nneg,
kw_disjoint,
+ kw_samesign,
kw_debug_location,
kw_debug_instr_number,
kw_dbg_instr_ref,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 45847b5830da65..059814c70f828d 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1476,7 +1476,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
Token.is(MIToken::kw_noconvergent) ||
Token.is(MIToken::kw_unpredictable) ||
Token.is(MIToken::kw_nneg) ||
- Token.is(MIToken::kw_disjoint)) {
+ Token.is(MIToken::kw_disjoint) ||
+ Token.is(MIToken::kw_samesign)) {
// clang-format on
// Mine frame and fast math flags
if (Token.is(MIToken::kw_frame_setup))
@@ -1513,6 +1514,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
Flags |= MachineInstr::NonNeg;
if (Token.is(MIToken::kw_disjoint))
Flags |= MachineInstr::Disjoint;
+ if (Token.is(MIToken::kw_samesign))
+ Flags |= MachineInstr::SameSign;
lex();
}
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index a015cd3c2a55f9..658bbe0e577e5c 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -837,6 +837,8 @@ void MIPrinter::print(const MachineInstr &MI) {
OS << "disjoint ";
if (MI.getFlag(MachineInstr::NoUSWrap))
OS << "nusw ";
+ if (MI.getFlag(MachineInstr::SameSign))
+ OS << "samesign ";
OS << TII->getName(MI.getOpcode());
if (I < E)
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index c1bd0bb5b7162e..943d0edf2f8019 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -620,6 +620,12 @@ uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
MIFlags |= MachineInstr::MIFlag::FmReassoc;
}
+ // Copy the samesign flag.
+ if (const auto *ICI = dyn_cast<ICmpInst>(&I)) {
+ if (ICI->hasSameSign())
+ MIFlags |= MachineInstr::MIFlag::SameSign;
+ }
+
if (I.getMetadata(LLVMContext::MD_unpredictable))
MIFlags |= MachineInstr::MIFlag::Unpredictable;
@@ -1770,6 +1776,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << "nneg ";
if (getFlag(MachineInstr::Disjoint))
OS << "disjoint ";
+ if (getFlag(MachineInstr::SameSign))
+ OS << "samesign ";
// Print the opcode name.
if (TII)
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 281d1578d0173a..9c7085cc7e7a83 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -1105,6 +1105,9 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
if (Flags.hasDisjoint())
MI->setFlag(MachineInstr::MIFlag::Disjoint);
+
+ if (Flags.hasSameSign())
+ MI->setFlag(MachineInstr::MIFlag::SameSign);
}
// Emit all of the actual operands of this instruction, adding them to the
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 203e80e36b46d9..6d1ff4aafe4fc0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3652,6 +3652,10 @@ void SelectionDAGBuilder::visitICmp(const ICmpInst &I) {
Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT);
}
+ SDNodeFlags Flags;
+ Flags.setSameSign(I.hasSameSign());
+ SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
+
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
I.getType());
setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 703efb70089742..580ff19065557b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -653,6 +653,9 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
if (getFlags().hasDisjoint())
OS << " disjoint";
+ if (getFlags().hasSameSign())
+ OS << " samesign";
+
if (getFlags().hasNonNeg())
OS << " nneg";
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-icmp-samesign.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-icmp-samesign.ll
new file mode 100644
index 00000000000000..1bf1c8d7119d16
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-icmp-samesign.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
+define i1 @icmp_samesign(i32 %a, i32 %b) {
+ ; CHECK-LABEL: name: icmp_samesign
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: %2:_(s1) = samesign G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %2(s1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ %res = icmp samesign ult i32 %a, %b
+ ret i1 %res
+}
+
+define <2 x i1> @icmp_samesign2(<2 x i32> %a, <2 x i32> %b) {
+ ; CHECK-LABEL: name: icmp_samesign2
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: %2:_(<2 x s1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %res = icmp samesign ult <2 x i32> %a, %b
+ ret <2 x i1> %res
+}
diff --git a/llvm/test/CodeGen/MIR/X86/icmp-samesign.mir b/llvm/test/CodeGen/MIR/X86/icmp-samesign.mir
new file mode 100644
index 00000000000000..b614784bd25077
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/icmp-samesign.mir
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -x mir -march=x86-64 -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+ define i1 @icmp_samesign(i32 %a, i32 %b) {
+ entry:
+ %res = icmp samesign ult i32 %a, %b
+ ret i1 %res
+ }
+
+...
+---
+name: icmp_samesign
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr32 }
+liveins:
+ - { reg: '$edi', virtual-reg: '%0' }
+ - { reg: '$esi', virtual-reg: '%1' }
+body: |
+ bb.0:
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: icmp_samesign
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %tmp0:_(s32) = COPY $edi
+ ; CHECK-NEXT: %tmp1:_(s32) = COPY $esi
+ ; CHECK-NEXT: %tmp4:_(s8) = samesign G_ICMP intpred(ult), %tmp0(s32), %tmp1
+ ; CHECK-NEXT: $al = COPY %tmp4(s8)
+ ; CHECK-NEXT: RET 0, implicit $al
+ %tmp0:_(s32) = COPY $edi
+ %tmp1:_(s32) = COPY $esi
+ %tmp4:_(s8) = samesign G_ICMP intpred(ult), %tmp0(s32), %tmp1
+ $al = COPY %tmp4(s8)
+ RET 0, implicit $al
+
+...
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