[llvm] 7f498a8 - [CostModel][LoopVectorize] Move some loop vectoriser tests (#113702)

via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 30 06:50:06 PDT 2024 

Author: David Sherwood
Date: 2024-10-30T13:50:02Z
New Revision: 7f498a865fd946bb92e592b31b41509073306ab3

URL: https://github.com/llvm/llvm-project/commit/7f498a865fd946bb92e592b31b41509073306ab3
DIFF: https://github.com/llvm/llvm-project/commit/7f498a865fd946bb92e592b31b41509073306ab3.diff

LOG: [CostModel][LoopVectorize] Move some loop vectoriser tests (#113702)

Many tests that were in test/Analysis/CostModel were actually
loop vectoriser tests. I've moved them as follows:

Analysis/CostModel/X86 -> Transforms/LoopVectorize/X86/CostModel
Analysis/CostModel/AArch64/arith-fp-frem.ll ->
  Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll

Added: 
    llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
    llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll

Modified: 
    

Removed: 
    llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
    llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/handle-iptr-with-data-layout-to-not-assert.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-8.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-5.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-7.ll
    llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-8.ll
    llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
    llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
    llvm/test/Analysis/CostModel/X86/masked-load-i16.ll
    llvm/test/Analysis/CostModel/X86/masked-load-i32.ll
    llvm/test/Analysis/CostModel/X86/masked-load-i64.ll
    llvm/test/Analysis/CostModel/X86/masked-load-i8.ll
    llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/masked-store-i16.ll
    llvm/test/Analysis/CostModel/X86/masked-store-i32.ll
    llvm/test/Analysis/CostModel/X86/masked-store-i64.ll
    llvm/test/Analysis/CostModel/X86/masked-store-i8.ll
    llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll
    llvm/test/Analysis/CostModel/X86/strided-load-i16.ll
    llvm/test/Analysis/CostModel/X86/strided-load-i32.ll
    llvm/test/Analysis/CostModel/X86/strided-load-i64.ll
    llvm/test/Analysis/CostModel/X86/strided-load-i8.ll


################################################################################
diff  --git a/llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
rename to llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll

diff  --git a/llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll

diff  --git a/llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/handle-iptr-with-data-layout-to-not-assert.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
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diff  --git a/llvm/test/Analysis/CostModel/X86/strided-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
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similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i32.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll

diff  --git a/llvm/test/Analysis/CostModel/X86/strided-load-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i64.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll

diff  --git a/llvm/test/Analysis/CostModel/X86/strided-load-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i8.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll

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