[llvm] f447cf1 - [CSKY] Fix some typos in CPU feature descriptions (NFC) (#105774)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 30 03:56:00 PDT 2024
Author: Alex Rønne Petersen
Date: 2024-10-30T06:55:57-04:00
New Revision: f447cf15b2fcf40e519633d4cd211bb4211bfc08
URL: https://github.com/llvm/llvm-project/commit/f447cf15b2fcf40e519633d4cd211bb4211bfc08
DIFF: https://github.com/llvm/llvm-project/commit/f447cf15b2fcf40e519633d4cd211bb4211bfc08.diff
LOG: [CSKY] Fix some typos in CPU feature descriptions (NFC) (#105774)
In Zig, we have a tool that updates our CPU model/feature data from
LLVM's. Noticed these typos when running it for LLVM 19.
Note: I don't have commit access.
Added:
Modified:
llvm/lib/Target/CSKY/CSKY.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
index 9809caa8bd8f65..f88daeed8d4215 100644
--- a/llvm/lib/Target/CSKY/CSKY.td
+++ b/llvm/lib/Target/CSKY/CSKY.td
@@ -97,28 +97,28 @@ def iHasFLOAT7E60 : Predicate<"Subtarget->hasFLOAT7E60()">,
"Support CSKY float7e60 instructions">;
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
- "Enable divide instrutions">;
+ "Enable divide instructions">;
def HasHWDiv : Predicate<"Subtarget->hasHardwareDivide()">,
AssemblerPredicate<(all_of FeatureHWDiv),
- "Enable divide instrutions">;
+ "Enable divide instructions">;
def FeatureSTM : SubtargetFeature<"multiple_stld", "HasSTM", "true",
- "Enable multiple load/store instrutions">;
+ "Enable multiple load/store instructions">;
def HasSTM : Predicate<"Subtarget->hasSTM()">,
AssemblerPredicate<(all_of FeatureSTM),
- "Enable multiple load/store instrutions">;
+ "Enable multiple load/store instructions">;
def FeaturePushPop : SubtargetFeature<"pushpop", "HasPushPop", "true",
- "Enable push/pop instrutions">;
+ "Enable push/pop instructions">;
def HasPushPop : Predicate<"Subtarget->hasPushPop()">,
AssemblerPredicate<(all_of FeaturePushPop),
- "Enable push/pop instrutions">;
+ "Enable push/pop instructions">;
def FeatureDSP
- : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instrutions">;
+ : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instructions">;
def HasDSP : Predicate<"Subtarget->hasDSP()">,
AssemblerPredicate<(all_of FeatureDSP),
- "Enable DSP instrutions">;
+ "Enable DSP instructions">;
def HasDSP1E2
: SubtargetFeature<"dsp1e2", "HasDSP1E2", "true", "Support CSKY dsp1e2 instructions">;
@@ -133,16 +133,16 @@ def iHasDSPE60 : Predicate<"Subtarget->hasDSPE60()">,
"Support CSKY dspe60 instructions">;
def FeatureDSPV2 : SubtargetFeature<"dspv2", "HasDSPV2", "true",
- "Enable DSP V2.0 instrutions">;
+ "Enable DSP V2.0 instructions">;
def HasDSPV2 : Predicate<"Subtarget->hasDSPV2()">,
AssemblerPredicate<(all_of FeatureDSPV2),
- "Enable DSP V2.0 instrutions">;
+ "Enable DSP V2.0 instructions">;
def FeatureDSP_Silan : SubtargetFeature<"dsp_silan", "HasDSP_Silan", "true",
- "Enable DSP Silan instrutions">;
+ "Enable DSP Silan instructions">;
def HasDSP_Silan : Predicate<"Subtarget->hasDSP_Silan()">,
AssemblerPredicate<(all_of FeatureDSP_Silan),
- "Enable DSP Silan instrutions">;
+ "Enable DSP Silan instructions">;
// Atomic Support
def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true",
@@ -232,11 +232,11 @@ def FeatureSoftTP : SubtargetFeature<"soft-tp", "ReadTPHard", "false",
"Disable TLS Pointer register">;
def FeatureIstack : SubtargetFeature<"istack", "EnableInterruptAttribute",
- "true", "Enable interrput attribute">;
+ "true", "Enable interrupt attribute">;
def EnableInterruptAttribute
: Predicate<"Subtarget->enableInterruptAttribute()">,
AssemblerPredicate<(all_of FeatureIstack),
- "Enable interrput attribute">;
+ "Enable interrupt attribute">;
def FeatureConstPool : SubtargetFeature<"constpool", "DumpConstPool", "true",
"Dump the constant pool by compiler">;
More information about the llvm-commits
mailing list