[llvm] [RISCV] Set a barrier between mask producer and user of V0 (PR #114012)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

@michaelmaitland I think @preames has answered your question perfectly, the aim of this patch is to reduce the live range **overlap** (yeah I should use this term) of mask registers.

> My question is why we need this? Shouldn't register pressure on the mask register class (which only has one register) achieve this result? It clearly doesn't, but why? Is there something else we could tweak here?

I'll try to answer these questions with my rough understanding. There are some problems with current implementation in LLVM:
1. When tracking register pressure, we don't track physical registers. This is not an issue I think.
2. We do have a RegisterClass for mask reigster (which is `VMV0`), but we don't use it in most RVV pseudos (only used in inline asm constraint and add/sub with carry instructions). We use physical register V0 directly and insert a `$v0 = COPY` before the use. @lukel97 and I have tried to do the same thing (replace V0 with `VMV0`: https://github.com/llvm/llvm-project/pull/88496) before, but we encountered the same fundamental issue that causes `error: ran out of registers during register allocation` because of early-clobber constraint. We can revisit this approach if we think it is the correct way.

Yes, as what I can see, I have to admit that this patch seems to be a compromise.

https://github.com/llvm/llvm-project/pull/114012