[llvm] [RISCV] Add OperandType for sew and vecpolicy operands. (PR #114168)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 29 20:14:23 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/114168
>From b5303f6e2a2e9517928ebeaac61316f30583e488 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 29 Oct 2024 19:24:37 -0700
Subject: [PATCH 1/2] [RISCV] Add OperandType for sew and vecpolicy operands.
---
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 6 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 6 +
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 146 +++++++++---------
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 12 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 4 +-
5 files changed, 96 insertions(+), 78 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index e18329c3d2dd49..e0e1abc62b5349 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -335,7 +335,11 @@ enum OperandType : unsigned {
OPERAND_FRMARG,
// Operand is a 3-bit rounding mode where only RTZ is valid.
OPERAND_RTZARG,
- OPERAND_LAST_RISCV_IMM = OPERAND_RTZARG,
+ // Vector policy operand.
+ OPERAND_VECPOLICY,
+ // Vector SEW operand.
+ OPERAND_SEW,
+ OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 20e531657eb286..8c3c1b85dc0c9d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2542,6 +2542,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_RTZARG:
Ok = Imm == RISCVFPRndMode::RTZ;
break;
+ case RISCVOp::OPERAND_VECPOLICY:
+ Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
+ break;
+ case RISCVOp::OPERAND_SEW:
+ Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
+ break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index af4f653f57afd5..30d61901d0554d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -84,6 +84,14 @@ def AVL : RegisterOperand<GPRNoX0> {
let OperandType = "OPERAND_AVL";
}
+def vecpolicy : RISCVOp {
+ let OperandType = "OPERAND_VECPOLICY";
+}
+
+def sew : RISCVOp {
+ let OperandType = "OPERAND_SEW";
+}
+
// X0 has special meaning for vsetvl/vsetvli.
// rd | rs1 | AVL value | Effect on vl
//--------------------------------------------------------------
@@ -764,8 +772,8 @@ class GetVTypePredicates<VTypeInfo vti> {
class VPseudoUSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew,
+ vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -782,7 +790,7 @@ class VPseudoUSLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -799,7 +807,7 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -816,7 +824,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1,
- VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$avl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -833,7 +841,7 @@ class VPseudoSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -850,7 +858,7 @@ class VPseudoSLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -872,7 +880,7 @@ class VPseudoILoadNoMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -895,7 +903,7 @@ class VPseudoILoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -912,7 +920,7 @@ class VPseudoILoadMask<VReg RetClass,
class VPseudoUSStoreNoMask<VReg StClass,
int EEW> :
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>,
+ (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -926,7 +934,7 @@ class VPseudoUSStoreMask<VReg StClass,
int EEW> :
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -940,7 +948,7 @@ class VPseudoSStoreNoMask<VReg StClass,
int EEW> :
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -954,7 +962,7 @@ class VPseudoSStoreMask<VReg StClass,
int EEW> :
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -967,7 +975,7 @@ class VPseudoSStoreMask<VReg StClass,
class VPseudoNullaryNoMask<VReg RegClass> :
Pseudo<(outs RegClass:$rd),
(ins RegClass:$passthru,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -981,7 +989,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
class VPseudoNullaryMask<VReg RegClass> :
Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
(ins GetVRegNoV0<RegClass>.R:$passthru,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -996,7 +1004,7 @@ class VPseudoNullaryMask<VReg RegClass> :
// Nullary for pseudo instructions. They are expanded in
// RISCVExpandPseudoInsts pass.
class VPseudoNullaryPseudoM<string BaseInst> :
- Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>,
+ Pseudo<(outs VR:$rd), (ins AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1016,7 +1024,7 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1033,7 +1041,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
+ (ins OpClass:$rs2, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1050,7 +1058,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1070,7 +1078,7 @@ class VPseudoUnaryMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1090,7 +1098,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1110,7 +1118,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1128,7 +1136,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1148,7 +1156,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1164,7 +1172,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
class VPseudoUnaryNoMaskGPROut :
Pseudo<(outs GPR:$rd),
- (ins VR:$rs2, AVL:$vl, ixlenimm:$sew), []>,
+ (ins VR:$rs2, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1175,7 +1183,7 @@ class VPseudoUnaryNoMaskGPROut :
class VPseudoUnaryMaskGPROut :
Pseudo<(outs GPR:$rd),
- (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1189,7 +1197,7 @@ class VPseudoUnaryAnyMask<VReg RetClass,
VReg Op1Class> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2,
- VR:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VR:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1205,7 +1213,7 @@ class VPseudoBinaryNoMask<VReg RetClass,
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
+ (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1223,7 +1231,7 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1243,7 +1251,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1266,7 +1274,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1288,8 +1296,8 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
+ vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1310,8 +1318,8 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1,
ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew,
+ vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1331,7 +1339,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
- ixlenimm:$sew),[]>,
+ sew:$sew),[]>,
RISCVVPseudo,
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
@@ -1345,7 +1353,7 @@ class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
RISCVVPseudo,
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
@@ -1363,7 +1371,7 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1382,7 +1390,7 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1401,7 +1409,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm,
ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1423,7 +1431,7 @@ class VPseudoBinaryMOutMask<VReg RetClass,
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1445,7 +1453,7 @@ class VPseudoTiedBinaryMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1468,7 +1476,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
Op2Class:$rs1,
VMaskOp:$vm,
ixlenimm:$rm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1494,9 +1502,9 @@ class VPseudoBinaryCarry<VReg RetClass,
Pseudo<(outs RetClass:$rd),
!if(CarryIn,
(ins Op1Class:$rs2, Op2Class:$rs1,
- VMV0:$carry, AVL:$vl, ixlenimm:$sew),
+ VMV0:$carry, AVL:$vl, sew:$sew),
(ins Op1Class:$rs2, Op2Class:$rs1,
- AVL:$vl, ixlenimm:$sew)), []>,
+ AVL:$vl, sew:$sew)), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1515,7 +1523,7 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
- VMV0:$carry, AVL:$vl, ixlenimm:$sew), []>,
+ VMV0:$carry, AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1534,7 +1542,7 @@ class VPseudoTernaryNoMask<VReg RetClass,
string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1551,7 +1559,7 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1570,7 +1578,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ ixlenimm:$rm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1589,7 +1597,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1606,7 +1614,7 @@ class VPseudoUSSegLoadMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1624,7 +1632,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1641,7 +1649,7 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ VMaskOp:$vm, AVL:$avl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1659,7 +1667,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1676,8 +1684,8 @@ class VPseudoSSegLoadMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
- GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
+ vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1698,7 +1706,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
bit Ordered> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
- ixlenimm:$sew, ixlenimm:$policy), []>,
+ sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -1720,8 +1728,8 @@ class VPseudoISegLoadMask<VReg RetClass,
bit Ordered> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
- IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew,
- ixlenimm:$policy), []>,
+ IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
+ vecpolicy:$policy), []>,
RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -1740,7 +1748,7 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>,
+ (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -1755,7 +1763,7 @@ class VPseudoUSSegStoreMask<VReg ValClass,
bits<4> NF> :
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -1770,7 +1778,7 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
bits<4> NF> :
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1, GPR:$offset,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -1785,7 +1793,7 @@ class VPseudoSSegStoreMask<VReg ValClass,
bits<4> NF> :
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1, GPR: $offset,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -1803,7 +1811,7 @@ class VPseudoISegStoreNoMask<VReg ValClass,
bit Ordered> :
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
@@ -1821,7 +1829,7 @@ class VPseudoISegStoreMask<VReg ValClass,
bit Ordered> :
Pseudo<(outs),
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 0;
@@ -6762,13 +6770,13 @@ let Predicates = [HasVInstructions] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S:
- Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>,
+ Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>,
Sched<[WriteVMovXS, ReadVMovXS]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,
Constraints = "$rd = $rs1" in
def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
- (ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),
+ (ins VR:$rs1, GPR:$rs2, AVL:$vl, sew:$sew),
[]>,
Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>,
RISCVVPseudo;
@@ -6785,14 +6793,14 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def "PseudoVFMV_" # f.FX # "_S" :
Pseudo<(outs f.fprclass:$rd),
- (ins VR:$rs2, ixlenimm:$sew), []>,
+ (ins VR:$rs2, sew:$sew), []>,
Sched<[WriteVMovFS, ReadVMovFS]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,
Constraints = "$rd = $rs1" in
def "PseudoVFMV_S_" # f.FX :
Pseudo<(outs VR:$rd),
- (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, ixlenimm:$sew),
+ (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, sew:$sew),
[]>,
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
RISCVVPseudo;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 5068d0be0fb49b..81467ada004487 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -230,7 +230,7 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf
class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
Pseudo<(outs),
(ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -243,7 +243,7 @@ class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
Pseudo<(outs),
(ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -257,7 +257,7 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
Pseudo<(outs),
(ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -270,7 +270,7 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
Pseudo<(outs RDClass:$rd),
(ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -284,7 +284,7 @@ class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
Pseudo<(outs RDClass:$rd),
(ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -298,7 +298,7 @@ class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
DAGOperand RS1Class> :
Pseudo<(outs RDClass:$rd),
(ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
- AVL:$vl, ixlenimm:$sew), []>,
+ AVL:$vl, sew:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 7ec13e4eaafa7d..92766a8670c48d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -231,7 +231,7 @@ class ZvkMxSet<string vd_lmul> {
class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
Pseudo<(outs RetClass:$rd_wb),
- (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -248,7 +248,7 @@ class VPseudoTernaryNoMask_Zvk<VReg RetClass,
DAGOperand Op2Class> :
Pseudo<(outs RetClass:$rd_wb),
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
>From dcbb655d20d8b04a0516cfc8c7ad6dfb65239869 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 29 Oct 2024 20:06:48 -0700
Subject: [PATCH 2/2] fixup! rename vecpolicy -> vec_policy.
---
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +-
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 78 +++++++++----------
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 4 +-
4 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index e0e1abc62b5349..d300a6309f9447 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -336,7 +336,7 @@ enum OperandType : unsigned {
// Operand is a 3-bit rounding mode where only RTZ is valid.
OPERAND_RTZARG,
// Vector policy operand.
- OPERAND_VECPOLICY,
+ OPERAND_VEC_POLICY,
// Vector SEW operand.
OPERAND_SEW,
OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 8c3c1b85dc0c9d..c1052c9fc77521 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2542,7 +2542,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_RTZARG:
Ok = Imm == RISCVFPRndMode::RTZ;
break;
- case RISCVOp::OPERAND_VECPOLICY:
+ case RISCVOp::OPERAND_VEC_POLICY:
Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
break;
case RISCVOp::OPERAND_SEW:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 30d61901d0554d..6ffdae1d7df2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -84,8 +84,8 @@ def AVL : RegisterOperand<GPRNoX0> {
let OperandType = "OPERAND_AVL";
}
-def vecpolicy : RISCVOp {
- let OperandType = "OPERAND_VECPOLICY";
+def vec_policy : RISCVOp {
+ let OperandType = "OPERAND_VEC_POLICY";
}
def sew : RISCVOp {
@@ -773,7 +773,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew,
- vecpolicy:$policy), []>,
+ vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -790,7 +790,7 @@ class VPseudoUSLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -807,7 +807,7 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -824,7 +824,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1,
- VMaskOp:$vm, AVL:$avl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -841,7 +841,7 @@ class VPseudoSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -858,7 +858,7 @@ class VPseudoSLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1, GPR:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -880,7 +880,7 @@ class VPseudoILoadNoMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -903,7 +903,7 @@ class VPseudoILoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
GPRMem:$rs1, IdxClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -975,7 +975,7 @@ class VPseudoSStoreMask<VReg StClass,
class VPseudoNullaryNoMask<VReg RegClass> :
Pseudo<(outs RegClass:$rd),
(ins RegClass:$passthru,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -989,7 +989,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
class VPseudoNullaryMask<VReg RegClass> :
Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
(ins GetVRegNoV0<RegClass>.R:$passthru,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1024,7 +1024,7 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1058,7 +1058,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1078,7 +1078,7 @@ class VPseudoUnaryMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1098,7 +1098,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$rm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1118,7 +1118,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []> {
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1136,7 +1136,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1156,7 +1156,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1231,7 +1231,7 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1251,7 +1251,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1274,7 +1274,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1297,7 +1297,7 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
- vecpolicy:$policy), []>,
+ vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1319,7 +1319,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
(ins RetClass:$rs2, Op2Class:$rs1,
ixlenimm:$rm,
AVL:$vl, sew:$sew,
- vecpolicy:$policy), []>,
+ vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1371,7 +1371,7 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1390,7 +1390,7 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op1Class:$rs2, Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1409,7 +1409,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm,
ixlenimm:$rm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1453,7 +1453,7 @@ class VPseudoTiedBinaryMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
Op2Class:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1476,7 +1476,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
Op2Class:$rs1,
VMaskOp:$vm,
ixlenimm:$rm,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1559,7 +1559,7 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1578,7 +1578,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
- ixlenimm:$rm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ ixlenimm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -1597,7 +1597,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1614,7 +1614,7 @@ class VPseudoUSSegLoadMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1632,7 +1632,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1649,7 +1649,7 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
- VMaskOp:$vm, AVL:$avl, sew:$sew, vecpolicy:$policy), []>,
+ VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1667,7 +1667,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
bits<4> NF> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1685,7 +1685,7 @@ class VPseudoSSegLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
- vecpolicy:$policy), []>,
+ vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1;
@@ -1706,7 +1706,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
bit Ordered> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
- sew:$sew, vecpolicy:$policy), []>,
+ sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
@@ -1729,7 +1729,7 @@ class VPseudoISegLoadMask<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
- vecpolicy:$policy), []>,
+ vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
let mayLoad = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 92766a8670c48d..782651fd6d0197 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -231,7 +231,7 @@ class ZvkMxSet<string vd_lmul> {
class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
Pseudo<(outs RetClass:$rd_wb),
- (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
@@ -248,7 +248,7 @@ class VPseudoTernaryNoMask_Zvk<VReg RetClass,
DAGOperand Op2Class> :
Pseudo<(outs RetClass:$rd_wb),
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
- AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
+ AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
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