[llvm] [llvm][TableGen] Allow physical registers in patterns for GlobalISel emitter (PR #113127)

[Matt Arsenault via llvm-commits]

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@@ -3,10 +3,34 @@
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
-// CHECK: Skipped pattern: Pattern defines a physical register
 let Uses = [B0], Defs = [B0] in
 def tst1 : I<(outs), (ins), [(set B0, (add B0, 1))]>;
 
-// CHECK: Skipped pattern: Src pattern result has 1 def(s) without the HasNoUse predicate set to true but Dst MI has no def
+// CHECK: Skipped pattern: unhandled discarded def
 let Uses = [B0] in
 def tst2 : I<(outs), (ins), [(set B0, (add B0, 1))]>;
+
+// test courtesy @s-barannikov
+def SDTBinOpWithFlagsOut : SDTypeProfile<2, 2, [
+  SDTCisInt<0>,       // result
+  SDTCisVT<1, i32>,   // out flags
+  SDTCisSameAs<2, 0>, // lhs
+  SDTCisSameAs<3, 0>  // rhs
+]>;
+
+def my_sub : SDNode<"MyTargetISD::SUB", SDTBinOpWithFlagsOut>;
+def my_ineg : PatFrag<(ops node:$val), (my_sub 0, node:$val)>;
+
+let Defs = [R1], Constraints = "$rd = $rs2" in
+def tst3 : I<(outs GPR32:$rd), (ins GPR32:$rs2), []>;
+
+// CHECK: Skipped pattern: Src pattern result has more defs than dst MI (2 def(s) vs 1 def(s))
+def : Pat<(my_ineg i32:$val), (tst3 i32:$val)>;
----------------
arsenm wrote:

Why is this failing to import? We should allow selecting instructions with unused implicit defs. e.g. you should be able to select an add-no-carry input node to an add-with-implicit-physreg-carry-out def, where the implicit physical def is dead and the main result is used for the virtual register output 

https://github.com/llvm/llvm-project/pull/113127