[llvm] [RISCV] Add OperandType to loadfpimm. (PR #114150)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/114150

This is represented in the MachineInstr and MCInst as a 5-bit unsigned immediate so we use OPERAND_UIMM5. If someone needs to know for sure its an FLI constant in the future we can break it out to a new type.

>From f237905c2245a7241efed9e6327bcee994382052 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 29 Oct 2024 16:32:08 -0700
Subject: [PATCH] [RISCV] Add OperandType to loadfpimm.

This is represented in the MachineInstr and MCInst as a 5-bit
unsigned immediate so we use OPERAND_UIMM5. If someone needs to know
for sure its an FLI constant in the future we can break it out to
a new type.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index f62a7e1221122b..6e2d55e4df9f35 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -35,6 +35,8 @@ def LoadFPImmOperand : AsmOperandClass {
 def loadfpimm : Operand<XLenVT> {
   let ParserMatchClass = LoadFPImmOperand;
   let PrintMethod = "printFPImmOperand";
+  let OperandType = "OPERAND_UIMM5";
+  let OperandNamespace = "RISCVOp";
 }
 
 def RTZArg : AsmOperandClass {