[llvm] [AArch64][SVE] Use INS when moving elements from bottom 128b of SVE type (PR #114034)

[Paul Walker via llvm-commits]

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@@ -7222,44 +7222,101 @@ def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
                    V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
           )>;
 
-multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
-                                ValueType VTScal, Instruction INS> {
-  def : Pat<(VT128 (vector_insert V128:$src,
-                        (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),
+// Insert an extracted vector element into a 128-bit Neon vector
+multiclass Neon_INS_elt_pattern_v128<ValueType VT128, ValueType VT64, ValueType VTSVE,
+                                     ValueType VTScal, Operand ExIdxTy, Instruction INS> {
+  // Extracting from the lower 128-bits of an SVE vector
+  def : Pat<(VT128 (vector_insert VT128:$Rn,
+                      (VTScal (vector_extract VTSVE:$Rm, (i64 ExIdxTy:$Immn))),
+                      (i64 imm:$Immd))),
+            (INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), ExIdxTy:$Immn)>;
+
+  // Extracting from another Neon vector
+  def : Pat<(VT128 (vector_insert V128:$Rn,
+                        (VTScal (vector_extract (VT128 V128:$Rm), (i64 imm:$Immn))),
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paulwalker-arm wrote:

This is a much bigger change than I was expecting.  A better starting point would be to add the two new patterns to `Neon_INS_elt_pattern` that match the existing ones but take an SVE input.  I think that will implement the majority of the ISEL you need.

The remaining part is likely to be the two patterns needed for the `v1{i,f}64 scalar_to_vector` case, which I'd put in `AArch64InstrInfo.td` near the existing `sext_inreg (vector_extract` patterns.

https://github.com/llvm/llvm-project/pull/114034