[llvm] [TableGen] Make `!and` short-circuit when either of the operand is zero (PR #113963)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

To give a little more background, this is the case (which is also the attached test case) that motivates me to come up with this patch:
```
class Foo <list<int> seq = []> {
   bit containsStr = !ne(!find(NAME, "BAR"), -1);
   list<int> newSeq  = !if(!and(!not(!empty(seq)), containsStr), !tail(seq), seq);
 }

 def rec8 : Foo<>;
```
Since the `!if` condition cannot be resolved immediately, TableGen resolver actually resolve both `!tail(seq)` and `seq` right away, and trigger an assertion in the process because `!tail` doesn't like `seq` being empty.

There are two ways to solve this problem: (1) Fix `!if` to postpone the resolution of its true and false values (2) make `!and` short-circuit.

I post this patch to do (2) first because I thought it can benefit more cases in addition to `!if` conditions. I'm thinking of posting a patch to do (1) as well and I'm happy to know what's your thought on that.

https://github.com/llvm/llvm-project/pull/113963