[llvm] [SDAG] Convert `SDNodeFlags` into an enumeration (PR #114061)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 29 07:26:39 PDT 2024
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/114061
This patch converts `SDNodeFlags` into an enumeration as we did for `FastMathFlags`. It simplifies the implementation and improves compile-time.
The first commit only modifies `SDNodeFlags` without changing its API.
The second commit allows using enumeration values directly and simplifies the implementation with bitwise logic. It addresses the comment in https://github.com/llvm/llvm-project/pull/113808#discussion_r1819923625.
Compile-time improvement: http://llvm-compile-time-tracker.com/compare.php?from=8e6856e27859c90c5337a8328848b0959fe409fe&to=b7de8427ff84035b7e5c9513d004d486918be605&stat=instructions%3Au
>From 59f61ebf43e056a26946fe508e6d2d781d243d52 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 29 Oct 2024 19:49:49 +0800
Subject: [PATCH 1/2] [SDAG] Convert `SDNodeFlags` into enums
---
llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 152 ++++++++----------
1 file changed, 66 insertions(+), 86 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index bda0120a2df4aa..77e6315ed2168e 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -378,36 +378,44 @@ template<> struct simplify_type<SDUse> {
/// the backend.
struct SDNodeFlags {
private:
- bool NoUnsignedWrap : 1;
- bool NoSignedWrap : 1;
- bool Exact : 1;
- bool Disjoint : 1;
- bool NonNeg : 1;
- bool NoNaNs : 1;
- bool NoInfs : 1;
- bool NoSignedZeros : 1;
- bool AllowReciprocal : 1;
- bool AllowContract : 1;
- bool ApproximateFuncs : 1;
- bool AllowReassociation : 1;
-
- // We assume instructions do not raise floating-point exceptions by default,
- // and only those marked explicitly may do so. We could choose to represent
- // this via a positive "FPExcept" flags like on the MI level, but having a
- // negative "NoFPExcept" flag here makes the flag intersection logic more
- // straightforward.
- bool NoFPExcept : 1;
- // Instructions with attached 'unpredictable' metadata on IR level.
- bool Unpredictable : 1;
+ friend class SDNode;
+
+ unsigned Flags = 0;
+
+ template <unsigned Flag> void setFlag(bool B) {
+ Flags = (Flags & ~Flag) | (B ? Flag : 0);
+ }
public:
+ enum {
+ NoUnsignedWrap = 1 << 0,
+ NoSignedWrap = 1 << 1,
+ Exact = 1 << 2,
+ Disjoint = 1 << 3,
+ NonNeg = 1 << 4,
+ NoNaNs = 1 << 5,
+ NoInfs = 1 << 6,
+ NoSignedZeros = 1 << 7,
+ AllowReciprocal = 1 << 8,
+ AllowContract = 1 << 9,
+ ApproximateFuncs = 1 << 10,
+ AllowReassociation = 1 << 11,
+
+ // We assume instructions do not raise floating-point exceptions by default,
+ // and only those marked explicitly may do so. We could choose to represent
+ // this via a positive "FPExcept" flags like on the MI level, but having a
+ // negative "NoFPExcept" flag here makes the flag intersection logic more
+ // straightforward.
+ NoFPExcept = 1 << 12,
+ // Instructions with attached 'unpredictable' metadata on IR level.
+ Unpredictable = 1 << 13,
+
+ PoisonGeneratingFlags = NoUnsignedWrap | NoSignedWrap | Exact | Disjoint |
+ NonNeg | NoNaNs | NoInfs,
+ };
+
/// Default constructor turns off all optimization flags.
- SDNodeFlags()
- : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false),
- Disjoint(false), NonNeg(false), NoNaNs(false), NoInfs(false),
- NoSignedZeros(false), AllowReciprocal(false), AllowContract(false),
- ApproximateFuncs(false), AllowReassociation(false), NoFPExcept(false),
- Unpredictable(false) {}
+ SDNodeFlags() : Flags(0) {}
/// Propagate the fast-math-flags from an IR FPMathOperator.
void copyFMF(const FPMathOperator &FPMO) {
@@ -421,69 +429,44 @@ struct SDNodeFlags {
}
// These are mutators for each flag.
- void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
- void setNoSignedWrap(bool b) { NoSignedWrap = b; }
- void setExact(bool b) { Exact = b; }
- void setDisjoint(bool b) { Disjoint = b; }
- void setNonNeg(bool b) { NonNeg = b; }
- void setNoNaNs(bool b) { NoNaNs = b; }
- void setNoInfs(bool b) { NoInfs = b; }
- void setNoSignedZeros(bool b) { NoSignedZeros = b; }
- void setAllowReciprocal(bool b) { AllowReciprocal = b; }
- void setAllowContract(bool b) { AllowContract = b; }
- void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
- void setAllowReassociation(bool b) { AllowReassociation = b; }
- void setNoFPExcept(bool b) { NoFPExcept = b; }
- void setUnpredictable(bool b) { Unpredictable = b; }
+ void setNoUnsignedWrap(bool b) { setFlag<NoUnsignedWrap>(b); }
+ void setNoSignedWrap(bool b) { setFlag<NoSignedWrap>(b); }
+ void setExact(bool b) { setFlag<Exact>(b); }
+ void setDisjoint(bool b) { setFlag<Disjoint>(b); }
+ void setNonNeg(bool b) { setFlag<NonNeg>(b); }
+ void setNoNaNs(bool b) { setFlag<NoNaNs>(b); }
+ void setNoInfs(bool b) { setFlag<NoInfs>(b); }
+ void setNoSignedZeros(bool b) { setFlag<NoSignedZeros>(b); }
+ void setAllowReciprocal(bool b) { setFlag<AllowReciprocal>(b); }
+ void setAllowContract(bool b) { setFlag<AllowContract>(b); }
+ void setApproximateFuncs(bool b) { setFlag<ApproximateFuncs>(b); }
+ void setAllowReassociation(bool b) { setFlag<AllowReassociation>(b); }
+ void setNoFPExcept(bool b) { setFlag<NoFPExcept>(b); }
+ void setUnpredictable(bool b) { setFlag<Unpredictable>(b); }
// These are accessors for each flag.
- bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
- bool hasNoSignedWrap() const { return NoSignedWrap; }
- bool hasExact() const { return Exact; }
- bool hasDisjoint() const { return Disjoint; }
- bool hasNonNeg() const { return NonNeg; }
- bool hasNoNaNs() const { return NoNaNs; }
- bool hasNoInfs() const { return NoInfs; }
- bool hasNoSignedZeros() const { return NoSignedZeros; }
- bool hasAllowReciprocal() const { return AllowReciprocal; }
- bool hasAllowContract() const { return AllowContract; }
- bool hasApproximateFuncs() const { return ApproximateFuncs; }
- bool hasAllowReassociation() const { return AllowReassociation; }
- bool hasNoFPExcept() const { return NoFPExcept; }
- bool hasUnpredictable() const { return Unpredictable; }
+ bool hasNoUnsignedWrap() const { return Flags & NoUnsignedWrap; }
+ bool hasNoSignedWrap() const { return Flags & NoSignedWrap; }
+ bool hasExact() const { return Flags & Exact; }
+ bool hasDisjoint() const { return Flags & Disjoint; }
+ bool hasNonNeg() const { return Flags & NonNeg; }
+ bool hasNoNaNs() const { return Flags & NoNaNs; }
+ bool hasNoInfs() const { return Flags & NoInfs; }
+ bool hasNoSignedZeros() const { return Flags & NoSignedZeros; }
+ bool hasAllowReciprocal() const { return Flags & AllowReciprocal; }
+ bool hasAllowContract() const { return Flags & AllowContract; }
+ bool hasApproximateFuncs() const { return Flags & ApproximateFuncs; }
+ bool hasAllowReassociation() const { return Flags & AllowReassociation; }
+ bool hasNoFPExcept() const { return Flags & NoFPExcept; }
+ bool hasUnpredictable() const { return Flags & Unpredictable; }
bool operator==(const SDNodeFlags &Other) const {
- return NoUnsignedWrap == Other.NoUnsignedWrap &&
- NoSignedWrap == Other.NoSignedWrap && Exact == Other.Exact &&
- Disjoint == Other.Disjoint && NonNeg == Other.NonNeg &&
- NoNaNs == Other.NoNaNs && NoInfs == Other.NoInfs &&
- NoSignedZeros == Other.NoSignedZeros &&
- AllowReciprocal == Other.AllowReciprocal &&
- AllowContract == Other.AllowContract &&
- ApproximateFuncs == Other.ApproximateFuncs &&
- AllowReassociation == Other.AllowReassociation &&
- NoFPExcept == Other.NoFPExcept &&
- Unpredictable == Other.Unpredictable;
+ return Flags == Other.Flags;
}
/// Clear any flags in this flag set that aren't also set in Flags. All
/// flags will be cleared if Flags are undefined.
- void intersectWith(const SDNodeFlags Flags) {
- NoUnsignedWrap &= Flags.NoUnsignedWrap;
- NoSignedWrap &= Flags.NoSignedWrap;
- Exact &= Flags.Exact;
- Disjoint &= Flags.Disjoint;
- NonNeg &= Flags.NonNeg;
- NoNaNs &= Flags.NoNaNs;
- NoInfs &= Flags.NoInfs;
- NoSignedZeros &= Flags.NoSignedZeros;
- AllowReciprocal &= Flags.AllowReciprocal;
- AllowContract &= Flags.AllowContract;
- ApproximateFuncs &= Flags.ApproximateFuncs;
- AllowReassociation &= Flags.AllowReassociation;
- NoFPExcept &= Flags.NoFPExcept;
- Unpredictable &= Flags.Unpredictable;
- }
+ void intersectWith(const SDNodeFlags Flags) { this->Flags &= Flags.Flags; }
};
/// Represents one node in the SelectionDAG.
@@ -1029,10 +1012,7 @@ END_TWO_BYTE_PACK()
void intersectFlagsWith(const SDNodeFlags Flags);
bool hasPoisonGeneratingFlags() const {
- SDNodeFlags Flags = getFlags();
- return Flags.hasNoUnsignedWrap() || Flags.hasNoSignedWrap() ||
- Flags.hasExact() || Flags.hasDisjoint() || Flags.hasNonNeg() ||
- Flags.hasNoNaNs() || Flags.hasNoInfs();
+ return Flags.Flags & SDNodeFlags::PoisonGeneratingFlags;
}
void setCFIType(uint32_t Type) { CFIType = Type; }
>From b7de8427ff84035b7e5c9513d004d486918be605 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 29 Oct 2024 20:41:43 +0800
Subject: [PATCH 2/2] [SDAG] Use bitwise logic instead of setter/getter
---
llvm/include/llvm/CodeGen/SDPatternMatch.h | 16 +---
llvm/include/llvm/CodeGen/SelectionDAG.h | 8 +-
llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 21 +++--
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 40 ++++------
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 7 +-
.../SelectionDAG/LegalizeIntegerTypes.cpp | 6 +-
.../SelectionDAG/LegalizeVectorOps.cpp | 12 +--
.../SelectionDAG/LegalizeVectorTypes.cpp | 4 +-
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 17 ++--
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 7 +-
.../CodeGen/SelectionDAG/TargetLowering.cpp | 77 +++++--------------
.../Target/AArch64/AArch64ISelLowering.cpp | 15 +---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 17 ++--
.../Target/SystemZ/SystemZISelLowering.cpp | 5 +-
.../CodeGen/SelectionDAGPatternMatchTest.cpp | 9 +--
16 files changed, 91 insertions(+), 172 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SDPatternMatch.h b/llvm/include/llvm/CodeGen/SDPatternMatch.h
index b3e249b7ebd5c4..96667952a16efc 100644
--- a/llvm/include/llvm/CodeGen/SDPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/SDPatternMatch.h
@@ -533,9 +533,7 @@ struct BinaryOpc_match {
if (!Flags.has_value())
return true;
- SDNodeFlags TmpFlags = *Flags;
- TmpFlags.intersectWith(N->getFlags());
- return TmpFlags == *Flags;
+ return (*Flags & N->getFlags()) == *Flags;
}
return false;
@@ -668,9 +666,7 @@ inline BinaryOpc_match<LHS, RHS, true> m_Or(const LHS &L, const RHS &R) {
template <typename LHS, typename RHS>
inline BinaryOpc_match<LHS, RHS, true> m_DisjointOr(const LHS &L,
const RHS &R) {
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
- return BinaryOpc_match<LHS, RHS, true>(ISD::OR, L, R, Flags);
+ return BinaryOpc_match<LHS, RHS, true>(ISD::OR, L, R, SDNodeFlags::Disjoint);
}
template <typename LHS, typename RHS>
@@ -813,9 +809,7 @@ template <typename Opnd_P, bool ExcludeChain = false> struct UnaryOpc_match {
if (!Flags.has_value())
return true;
- SDNodeFlags TmpFlags = *Flags;
- TmpFlags.intersectWith(N->getFlags());
- return TmpFlags == *Flags;
+ return (*Flags & N->getFlags()) == *Flags;
}
return false;
@@ -848,9 +842,7 @@ template <typename Opnd> inline UnaryOpc_match<Opnd> m_ZExt(const Opnd &Op) {
template <typename Opnd>
inline UnaryOpc_match<Opnd> m_NNegZExt(const Opnd &Op) {
- SDNodeFlags Flags;
- Flags.setNonNeg(true);
- return UnaryOpc_match<Opnd>(ISD::ZERO_EXTEND, Op, Flags);
+ return UnaryOpc_match<Opnd>(ISD::ZERO_EXTEND, Op, SDNodeFlags::NonNeg);
}
template <typename Opnd> inline auto m_SExt(const Opnd &Op) {
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index e82bdb6906163c..db111b0875a6ee 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1064,17 +1064,13 @@ class SelectionDAG {
/// addressing some offset of an object. i.e. if a load is split into multiple
/// components, create an add nuw from the base pointer to the offset.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) {
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
- return getMemBasePlusOffset(Ptr, Offset, SL, Flags);
+ return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
}
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) {
// The object itself can't wrap around the address space, so it shouldn't be
// possible for the adds of the offsets to the split parts to overflow.
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
- return getMemBasePlusOffset(Ptr, Offset, SL, Flags);
+ return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
}
/// Return a new CALLSEQ_START node, that starts new call frame, in which
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 77e6315ed2168e..91850c699ecbff 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -388,8 +388,10 @@ struct SDNodeFlags {
public:
enum {
+ None = 0,
NoUnsignedWrap = 1 << 0,
NoSignedWrap = 1 << 1,
+ NoWrap = NoUnsignedWrap | NoSignedWrap,
Exact = 1 << 2,
Disjoint = 1 << 3,
NonNeg = 1 << 4,
@@ -415,7 +417,7 @@ struct SDNodeFlags {
};
/// Default constructor turns off all optimization flags.
- SDNodeFlags() : Flags(0) {}
+ SDNodeFlags(unsigned Flags = SDNodeFlags::None) : Flags(Flags) {}
/// Propagate the fast-math-flags from an IR FPMathOperator.
void copyFMF(const FPMathOperator &FPMO) {
@@ -463,12 +465,20 @@ struct SDNodeFlags {
bool operator==(const SDNodeFlags &Other) const {
return Flags == Other.Flags;
}
-
- /// Clear any flags in this flag set that aren't also set in Flags. All
- /// flags will be cleared if Flags are undefined.
- void intersectWith(const SDNodeFlags Flags) { this->Flags &= Flags.Flags; }
+ void operator&=(const SDNodeFlags &OtherFlags) { Flags &= OtherFlags.Flags; }
+ void operator|=(const SDNodeFlags &OtherFlags) { Flags |= OtherFlags.Flags; }
};
+inline SDNodeFlags operator|(SDNodeFlags LHS, SDNodeFlags RHS) {
+ LHS |= RHS;
+ return LHS;
+}
+
+inline SDNodeFlags operator&(SDNodeFlags LHS, SDNodeFlags RHS) {
+ LHS &= RHS;
+ return LHS;
+}
+
/// Represents one node in the SelectionDAG.
///
class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
@@ -1006,6 +1016,7 @@ END_TWO_BYTE_PACK()
SDNodeFlags getFlags() const { return Flags; }
void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
+ void clearFlags(unsigned Mask) { Flags &= ~Mask; }
/// Clear any flags in this node that aren't also set in Flags.
/// If Flags is not in a defined state then this has no effect.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b800204d917503..c5d8af102123db 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1210,7 +1210,7 @@ SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
SDNodeFlags NewFlags;
if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() &&
Flags.hasNoUnsignedWrap())
- NewFlags.setNoUnsignedWrap(true);
+ NewFlags = SDNodeFlags::NoUnsignedWrap;
if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
// Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
@@ -2892,11 +2892,11 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
if (N->getFlags().hasNoUnsignedWrap() &&
N0->getFlags().hasNoUnsignedWrap() &&
N0.getOperand(0)->getFlags().hasNoUnsignedWrap()) {
- Flags.setNoUnsignedWrap(true);
+ Flags = SDNodeFlags::NoUnsignedWrap;
if (N->getFlags().hasNoSignedWrap() &&
N0->getFlags().hasNoSignedWrap() &&
N0.getOperand(0)->getFlags().hasNoSignedWrap())
- Flags.setNoSignedWrap(true);
+ Flags |= SDNodeFlags::NoSignedWrap;
}
SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N1), VT, A,
DAG.getConstant(CM, DL, VT), Flags);
@@ -2920,12 +2920,12 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
N0->getFlags().hasNoUnsignedWrap() &&
OMul->getFlags().hasNoUnsignedWrap() &&
OMul.getOperand(0)->getFlags().hasNoUnsignedWrap()) {
- Flags.setNoUnsignedWrap(true);
+ Flags = SDNodeFlags::NoUnsignedWrap;
if (N->getFlags().hasNoSignedWrap() &&
N0->getFlags().hasNoSignedWrap() &&
OMul->getFlags().hasNoSignedWrap() &&
OMul.getOperand(0)->getFlags().hasNoSignedWrap())
- Flags.setNoSignedWrap(true);
+ Flags |= SDNodeFlags::NoSignedWrap;
}
SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N1), VT, A,
DAG.getConstant(CM, DL, VT), Flags);
@@ -2987,11 +2987,8 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
// fold (a+b) -> (a|b) iff a and b share no bits.
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
- DAG.haveNoCommonBitsSet(N0, N1)) {
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
- return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags);
- }
+ DAG.haveNoCommonBitsSet(N0, N1))
+ return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
// Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
@@ -9547,11 +9544,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
// fold (a^b) -> (a|b) iff a and b share no bits.
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
- DAG.haveNoCommonBitsSet(N0, N1)) {
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
- return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags);
- }
+ DAG.haveNoCommonBitsSet(N0, N1))
+ return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
// look for 'add-like' folds:
// XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE)
@@ -10201,7 +10195,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
SDNodeFlags Flags;
// Preserve the disjoint flag for Or.
if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
- Flags.setDisjoint(true);
+ Flags = SDNodeFlags::Disjoint;
return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
}
}
@@ -13913,11 +13907,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// fold (sext x) -> (zext x) if the sign bit is known zero.
if (!TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) &&
(!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
- DAG.SignBitIsZero(N0)) {
- SDNodeFlags Flags;
- Flags.setNonNeg(true);
- return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0, Flags);
- }
+ DAG.SignBitIsZero(N0))
+ return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0, SDNodeFlags::NonNeg);
if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N))
return NewVSel;
@@ -14798,10 +14789,9 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
uint64_t PtrOff = PtrAdjustmentInBits / 8;
SDLoc DL(LN0);
// The original load itself didn't wrap, so an offset within it doesn't.
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
- SDValue NewPtr = DAG.getMemBasePlusOffset(
- LN0->getBasePtr(), TypeSize::getFixed(PtrOff), DL, Flags);
+ SDValue NewPtr =
+ DAG.getMemBasePlusOffset(LN0->getBasePtr(), TypeSize::getFixed(PtrOff),
+ DL, SDNodeFlags::NoUnsignedWrap);
AddToWorklist(NewPtr.getNode());
SDValue Load;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index e0a03383358b76..a139c5251cded8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1697,12 +1697,9 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
}
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
-
// Store the part with the modified sign and convert back to float.
- SDValue CopiedSign =
- DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit, Flags);
+ SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit,
+ SDNodeFlags::Disjoint);
return modifySignAsInt(MagAsInt, DL, CopiedSign);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index ee9c95c8593766..45487c887b74dd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -4674,9 +4674,9 @@ void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
DAG.getNode(ISD::SHL, dl, ShAmtVT, SrlTmp,
DAG.getConstant(Log2_32(ShiftUnitInBits), dl, ShAmtVT));
- Flags.setExact(true);
- SDValue ByteOffset = DAG.getNode(ISD::SRL, dl, ShAmtVT, BitOffset,
- DAG.getConstant(3, dl, ShAmtVT), Flags);
+ SDValue ByteOffset =
+ DAG.getNode(ISD::SRL, dl, ShAmtVT, BitOffset,
+ DAG.getConstant(3, dl, ShAmtVT), SDNodeFlags::Exact);
// And clamp it, because OOB load is an immediate UB,
// while shift overflow would have *just* been poison.
ByteOffset = DAG.getNode(ISD::AND, dl, ShAmtVT, ByteOffset,
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index a8042fc3e7a69a..89d61416e575b1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -1699,11 +1699,8 @@ SDValue VectorLegalizer::ExpandVP_FCOPYSIGN(SDNode *Node) {
SDValue ClearedSign =
DAG.getNode(ISD::VP_AND, DL, IntVT, Mag, ClearSignMask, Mask, EVL);
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
-
SDValue CopiedSign = DAG.getNode(ISD::VP_OR, DL, IntVT, ClearedSign, SignBit,
- Mask, EVL, Flags);
+ Mask, EVL, SDNodeFlags::Disjoint);
return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
}
@@ -1885,11 +1882,8 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT);
SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, Mag, ClearSignMask);
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
-
- SDValue CopiedSign =
- DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit, Flags);
+ SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit,
+ SDNodeFlags::Disjoint);
return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 50e2a923699c8a..bdc4755b5e6ca0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1377,16 +1377,14 @@ void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT,
unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinValue() / 8;
if (MemVT.isScalableVector()) {
- SDNodeFlags Flags;
SDValue BytesIncrement = DAG.getVScale(
DL, Ptr.getValueType(),
APInt(Ptr.getValueSizeInBits().getFixedValue(), IncrementSize));
MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace());
- Flags.setNoUnsignedWrap(true);
if (ScaledOffset)
*ScaledOffset += IncrementSize;
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, BytesIncrement,
- Flags);
+ SDNodeFlags::NoUnsignedWrap);
} else {
MPI = N->getPointerInfo().getWithOffset(IncrementSize);
// Increment the pointer to the other half.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1a86b3b51234d1..571fdffda2dc0f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -12377,7 +12377,7 @@ bool SDNode::hasPredecessor(const SDNode *N) const {
}
void SDNode::intersectFlagsWith(const SDNodeFlags Flags) {
- this->Flags.intersectWith(Flags);
+ this->Flags &= Flags;
}
SDValue
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 8450553743074c..f227d6ce4f206c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4318,7 +4318,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
SDNodeFlags Flags;
if (NW.hasNoUnsignedWrap() ||
(int64_t(Offset) >= 0 && NW.hasNoUnsignedSignedWrap()))
- Flags.setNoUnsignedWrap(true);
+ Flags = SDNodeFlags::NoUnsignedWrap;
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
DAG.getConstant(Offset, dl, N.getValueType()), Flags);
@@ -4484,10 +4484,9 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
// Round the size of the allocation up to the stack alignment size
// by add SA-1 to the size. This doesn't overflow because we're computing
// an address inside an alloca.
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize,
- DAG.getConstant(StackAlignMask, dl, IntPtr), Flags);
+ DAG.getConstant(StackAlignMask, dl, IntPtr),
+ SDNodeFlags::NoUnsignedWrap);
// Mask out the low bits for alignment purposes.
AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize,
@@ -11212,15 +11211,13 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
// An aggregate return value cannot wrap around the address space, so
// offsets to its parts don't wrap either.
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
-
MachineFunction &MF = CLI.DAG.getMachineFunction();
Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx);
for (unsigned i = 0; i < NumValues; ++i) {
- SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
- CLI.DAG.getConstant(Offsets[i], CLI.DL,
- PtrVT), Flags);
+ SDValue Add =
+ CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
+ CLI.DAG.getConstant(Offsets[i], CLI.DL, PtrVT),
+ SDNodeFlags::NoUnsignedWrap);
SDValue L = CLI.DAG.getLoad(
RetTys[i], CLI.DL, CLI.Chain, Add,
MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 981ab18b59c1c1..0d99ae9cdebd50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4224,11 +4224,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// Set the NoFPExcept flag when no original matched node could
// raise an FP exception, but the new node potentially might.
- if (!MayRaiseFPException && mayRaiseFPException(Res)) {
- SDNodeFlags Flags = Res->getFlags();
- Flags.setNoFPExcept(true);
- Res->setFlags(Flags);
- }
+ if (!MayRaiseFPException && mayRaiseFPException(Res))
+ Res->setFlags(Res->getFlags() | SDNodeFlags::NoFPExcept);
// If the node had chain/glue results, update our notion of the current
// chain and glue.
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 758b3a5fc526e7..e727cc33027d97 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1489,19 +1489,13 @@ bool TargetLowering::SimplifyDemandedBits(
SDNodeFlags Flags = Op.getNode()->getFlags();
if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
Depth + 1)) {
- if (Flags.hasDisjoint()) {
- Flags.setDisjoint(false);
- Op->setFlags(Flags);
- }
+ Op->clearFlags(SDNodeFlags::Disjoint);
return true;
}
if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
Known2, TLO, Depth + 1)) {
- if (Flags.hasDisjoint()) {
- Flags.setDisjoint(false);
- Op->setFlags(Flags);
- }
+ Op->clearFlags(SDNodeFlags::Disjoint);
return true;
}
@@ -1806,14 +1800,9 @@ bool TargetLowering::SimplifyDemandedBits(
APInt InDemandedMask = DemandedBits.lshr(ShAmt);
if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
Depth + 1)) {
- SDNodeFlags Flags = Op.getNode()->getFlags();
- if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
- // Disable the nsw and nuw flags. We can no longer guarantee that we
- // won't wrap after simplification.
- Flags.setNoSignedWrap(false);
- Flags.setNoUnsignedWrap(false);
- Op->setFlags(Flags);
- }
+ // Disable the nsw and nuw flags. We can no longer guarantee that we
+ // won't wrap after simplification.
+ Op->clearFlags(SDNodeFlags::NoWrap);
return true;
}
Known.Zero <<= ShAmt;
@@ -1897,14 +1886,9 @@ bool TargetLowering::SimplifyDemandedBits(
APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ));
if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO,
Depth + 1)) {
- SDNodeFlags Flags = Op.getNode()->getFlags();
- if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
- // Disable the nsw and nuw flags. We can no longer guarantee that we
- // won't wrap after simplification.
- Flags.setNoSignedWrap(false);
- Flags.setNoUnsignedWrap(false);
- Op->setFlags(Flags);
- }
+ // Disable the nsw and nuw flags. We can no longer guarantee that we
+ // won't wrap after simplification.
+ Op->clearFlags(SDNodeFlags::NoWrap);
return true;
}
Known.resetAll();
@@ -2456,15 +2440,11 @@ bool TargetLowering::SimplifyDemandedBits(
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
}
- SDNodeFlags Flags = Op->getFlags();
APInt InDemandedBits = DemandedBits.trunc(InBits);
APInt InDemandedElts = DemandedElts.zext(InElts);
if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
Depth + 1)) {
- if (Flags.hasNonNeg()) {
- Flags.setNonNeg(false);
- Op->setFlags(Flags);
- }
+ Op->clearFlags(SDNodeFlags::NonNeg);
return true;
}
assert(Known.getBitWidth() == InBits && "Src width has changed?");
@@ -2528,7 +2508,7 @@ bool TargetLowering::SimplifyDemandedBits(
if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) {
SDNodeFlags Flags;
if (!IsVecInReg)
- Flags.setNonNeg(true);
+ Flags = SDNodeFlags::NonNeg;
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src, Flags));
}
}
@@ -2836,13 +2816,9 @@ bool TargetLowering::SimplifyDemandedBits(
DemandedElts, KnownOp0, TLO, Depth + 1) ||
// See if the operation should be performed at a smaller bit width.
ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) {
- if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
- // Disable the nsw and nuw flags. We can no longer guarantee that we
- // won't wrap after simplification.
- Flags.setNoSignedWrap(false);
- Flags.setNoUnsignedWrap(false);
- Op->setFlags(Flags);
- }
+ // Disable the nsw and nuw flags. We can no longer guarantee that we
+ // won't wrap after simplification.
+ Op->clearFlags(SDNodeFlags::NoWrap);
return true;
}
@@ -2858,12 +2834,10 @@ bool TargetLowering::SimplifyDemandedBits(
SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1);
if (DemandedOp0 || DemandedOp1) {
- Flags.setNoSignedWrap(false);
- Flags.setNoUnsignedWrap(false);
Op0 = DemandedOp0 ? DemandedOp0 : Op0;
Op1 = DemandedOp1 ? DemandedOp1 : Op1;
- SDValue NewOp =
- TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
+ SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1,
+ Flags & ~SDNodeFlags::NoWrap);
return TLO.CombineTo(Op, NewOp);
}
}
@@ -2880,9 +2854,8 @@ bool TargetLowering::SimplifyDemandedBits(
SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT);
// Disable the nsw and nuw flags. We can no longer guarantee that we
// won't wrap after simplification.
- Flags.setNoSignedWrap(false);
- Flags.setNoUnsignedWrap(false);
- SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
+ SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1,
+ Flags & ~SDNodeFlags::NoWrap);
return TLO.CombineTo(Op, NewOp);
}
@@ -6157,9 +6130,7 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
SDValue Res = Op0;
if (UseSRA) {
- SDNodeFlags Flags;
- Flags.setExact(true);
- Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
+ Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, SDNodeFlags::Exact);
Created.push_back(Res.getNode());
}
@@ -6220,9 +6191,7 @@ static SDValue BuildExactUDIV(const TargetLowering &TLI, SDNode *N,
SDValue Res = N->getOperand(0);
if (UseSRL) {
- SDNodeFlags Flags;
- Flags.setExact(true);
- Res = DAG.getNode(ISD::SRL, dl, VT, Res, Shift, Flags);
+ Res = DAG.getNode(ISD::SRL, dl, VT, Res, Shift, SDNodeFlags::Exact);
Created.push_back(Res.getNode());
}
@@ -8447,9 +8416,7 @@ TargetLowering::createSelectForFMINNUM_FMAXNUM(SDNode *Node,
SDValue SelCC = DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred);
// Copy FMF flags, but always set the no-signed-zeros flag
// as this is implied by the FMINNUM/FMAXNUM semantics.
- SDNodeFlags Flags = Node->getFlags();
- Flags.setNoSignedZeros(true);
- SelCC->setFlags(Flags);
+ SelCC->setFlags(Node->getFlags() | SDNodeFlags::NoSignedZeros);
return SelCC;
}
@@ -11805,10 +11772,8 @@ SDValue TargetLowering::expandVECTOR_COMPRESS(SDNode *Node,
// Re-write the last ValI if all lanes were selected. Otherwise,
// overwrite the last write it with the passthru value.
- SDNodeFlags Flags{};
- Flags.setUnpredictable(true);
LastWriteVal = DAG.getSelect(DL, ScalarVT, AllLanesSelected, ValI,
- LastWriteVal, Flags);
+ LastWriteVal, SDNodeFlags::Unpredictable);
Chain = DAG.getStore(
Chain, DL, LastWriteVal, OutPtr,
MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 32ba2866ac8180..0fe3c849eb14a3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7922,10 +7922,8 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize), DL,
Ptr.getValueType());
}
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
- BytesIncrement, Flags);
+ BytesIncrement, SDNodeFlags::NoUnsignedWrap);
ExtraArgLocs++;
i++;
}
@@ -8981,12 +8979,9 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize), DL,
Ptr.getValueType());
}
- SDNodeFlags Flags;
- Flags.setNoUnsignedWrap(true);
-
MPI = MachinePointerInfo(MPI.getAddrSpace());
Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
- BytesIncrement, Flags);
+ BytesIncrement, SDNodeFlags::NoUnsignedWrap);
ExtraArgLocs++;
i++;
}
@@ -11772,8 +11767,7 @@ SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand,
SDLoc DL(Operand);
EVT VT = Operand.getValueType();
- SDNodeFlags Flags;
- Flags.setAllowReassociation(true);
+ SDNodeFlags Flags = SDNodeFlags::AllowReassociation;
// Newton reciprocal square root iteration: E * 0.5 * (3 - X * E^2)
// AArch64 reciprocal square root iteration instruction: 0.5 * (3 - M * N)
@@ -11802,8 +11796,7 @@ SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,
SDLoc DL(Operand);
EVT VT = Operand.getValueType();
- SDNodeFlags Flags;
- Flags.setAllowReassociation(true);
+ SDNodeFlags Flags = SDNodeFlags::AllowReassociation;
// Newton reciprocal iteration: E * (2 - X * E)
// AArch64 reciprocal iteration instruction: (2 - M * N)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index af7a39b2580a37..e7898747fcce90 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3990,10 +3990,9 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
B = DAG.getNode(ISD::AND, SDLoc(B), XLenVT, B, Mask);
SDValue ShtAmt = DAG.getConstant(ElemSizeInBits, ElemDL, XLenVT);
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
return DAG.getNode(ISD::OR, ElemDL, XLenVT, A,
- DAG.getNode(ISD::SHL, ElemDL, XLenVT, B, ShtAmt), Flags);
+ DAG.getNode(ISD::SHL, ElemDL, XLenVT, B, ShtAmt),
+ SDNodeFlags::Disjoint);
};
SmallVector<SDValue> NewOperands;
@@ -6022,11 +6021,8 @@ static SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG,
SDValue ClearedSign =
DAG.getNode(ISD::AND, DL, XLenVT, MagAsInt, ClearSignMask);
- SDNodeFlags Flags;
- Flags.setDisjoint(true);
-
- SDValue CopiedSign =
- DAG.getNode(ISD::OR, DL, XLenVT, ClearedSign, SignBit, Flags);
+ SDValue CopiedSign = DAG.getNode(ISD::OR, DL, XLenVT, ClearedSign, SignBit,
+ SDNodeFlags::Disjoint);
return DAG.getNode(RISCVISD::FMV_H_X, DL, VT, CopiedSign);
}
@@ -13291,9 +13287,8 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG,
EVT ReduceVT = EVT::getVectorVT(*DAG.getContext(), VT, RHSIdx + 1);
SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec,
DAG.getVectorIdxConstant(0, DL));
- auto Flags = ReduceVec->getFlags();
- Flags.intersectWith(N->getFlags());
- return DAG.getNode(ReduceOpc, DL, VT, Vec, Flags);
+ return DAG.getNode(ReduceOpc, DL, VT, Vec,
+ ReduceVec->getFlags() & N->getFlags());
}
return SDValue();
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 1fa2dbfb26fc25..52526d54c86d90 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2676,10 +2676,7 @@ static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
(N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
// Disable the nsw and nuw flags: the backend needs to handle
// overflow as well during comparison elimination.
- SDNodeFlags Flags = N->getFlags();
- Flags.setNoSignedWrap(false);
- Flags.setNoUnsignedWrap(false);
- N->setFlags(Flags);
+ N->clearFlags(SDNodeFlags::NoWrap);
C.Op0 = SDValue(N, 0);
C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
return;
diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
index dc40e5893b65e2..1402c1d5b1398b 100644
--- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
@@ -193,9 +193,8 @@ TEST_F(SelectionDAGPatternMatchTest, matchBinaryOp) {
SDValue And = DAG->getNode(ISD::AND, DL, Int32VT, Op0, Op1);
SDValue Xor = DAG->getNode(ISD::XOR, DL, Int32VT, Op1, Op0);
SDValue Or = DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op1);
- SDNodeFlags DisFlags;
- DisFlags.setDisjoint(true);
- SDValue DisOr = DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op3, DisFlags);
+ SDValue DisOr =
+ DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op3, SDNodeFlags::Disjoint);
SDValue SMax = DAG->getNode(ISD::SMAX, DL, Int32VT, Op0, Op1);
SDValue SMin = DAG->getNode(ISD::SMIN, DL, Int32VT, Op1, Op0);
SDValue UMax = DAG->getNode(ISD::UMAX, DL, Int32VT, Op0, Op1);
@@ -293,10 +292,8 @@ TEST_F(SelectionDAGPatternMatchTest, matchUnaryOp) {
SDValue Op3 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 3, Int32VT);
SDValue ZExt = DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op0);
- SDNodeFlags NNegFlags;
- NNegFlags.setNonNeg(true);
SDValue ZExtNNeg =
- DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op3, NNegFlags);
+ DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op3, SDNodeFlags::NonNeg);
SDValue SExt = DAG->getNode(ISD::SIGN_EXTEND, DL, Int64VT, Op0);
SDValue Trunc = DAG->getNode(ISD::TRUNCATE, DL, Int32VT, Op1);
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