[llvm] 98c8d64 - [AArch64] Add assembly/dissasembly for BFSCALE instructions (#113538)
via llvm-commits
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Tue Oct 29 04:08:40 PDT 2024
Author: Lukacma
Date: 2024-10-29T11:08:36Z
New Revision: 98c8d643539194321f3dba8698e95999165b1024
URL: https://github.com/llvm/llvm-project/commit/98c8d643539194321f3dba8698e95999165b1024
DIFF: https://github.com/llvm/llvm-project/commit/98c8d643539194321f3dba8698e95999165b1024.diff
LOG: [AArch64] Add assembly/dissasembly for BFSCALE instructions (#113538)
This patch adds assembly/disassembly for following instructions:
BFSCALE (multiple and single vector)
BFSCALE (multiple vectors)
As specified in https://developer.arm.com/documentation/ddi0602/2024-09
Co-authored-by: Momchil Velikov
[momchil.velikov at arm.com](mailto:momchil.velikov at arm.com)
Added:
llvm/test/MC/AArch64/SME2/bfscale-diagnostics.s
llvm/test/MC/AArch64/SME2/bfscale.s
Modified:
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 76e0501a5cc233..b0ce9e1a1b406f 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -1000,6 +1000,11 @@ defm FMOPA_MPPZZ_BtoS : sme_outer_product_fp32<0b0, 0b01, ZPR8, "fmopa", null_fr
} //[HasSMEF8F32]
+let Predicates = [HasSME2, HasSVEBFSCALE] in {
+ defm BFSCALE : sme2_bfscale_single<"bfscale">;
+ defm BFSCALE : sme2_bfscale_multi<"bfscale">;
+}
+
let Predicates = [HasSME2p2] in {
def FTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b11000, ZZ_h_mul_r, ZPR16, "ftmopa">;
def FTMOPA_M2ZZZI_StoS : sme_tmopa_32b<0b00000, ZZ_s_mul_r, ZPR32, "ftmopa">;
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index a05c5206320f71..62a0c2e83d4a2e 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -5189,6 +5189,16 @@ class sme2_luti4_vector_vg4_strided<bits<2> sz, bits<2> op, string mnemonic>
let Inst{1-0} = Zd{1-0};
}
+multiclass sme2_bfscale_single<string mnemonic> {
+ def _2ZZ : sme2_sve_destructive_vector_vg2_single<0b00, 0b0011000, ZZ_h_mul_r, ZPR4b16, mnemonic>;
+ def _4ZZ : sme2_sve_destructive_vector_vg4_single<0b00, 0b0011000, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
+}
+
+multiclass sme2_bfscale_multi<string mnemonic> {
+ def _2Z2Z : sme2_sve_destructive_vector_vg2_multi<0b00, 0b0011000, ZZ_h_mul_r, mnemonic>;
+ def _4Z4Z : sme2_sve_destructive_vector_vg4_multi<0b00, 0b0011000, ZZZZ_h_mul_r, mnemonic>;
+}
+
class sme2_bf16_fp32_quarter_tile_outer_product<bit M, bit N, bit S, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
: I<(outs TileOp32:$ZAda),
(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
@@ -5334,4 +5344,4 @@ multiclass sme2_multi4_fmul_mm<string mnemonic> {
multiclass sme2_bfmul_multi<string mnemonic> {
def _2Z2Z : sme2_multi2_fmul_mm<0b00, mnemonic, ZZ_h_mul_r>;
def _4Z4Z : sme2_multi4_fmul_mm<0b00, mnemonic, ZZZZ_h_mul_r>;
-}
+}
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2/bfscale-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfscale-diagnostics.s
new file mode 100644
index 00000000000000..63367eed65b6c9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfscale-diagnostics.s
@@ -0,0 +1,87 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale 2>&1 < %s| FileCheck %s
+
+// Multiple and single vector, 2 regs
+
+bfscale {z0.s-z1.s}, {z0.s-z1.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z1.h-z2.h}, {z1.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfscale {z0.h-z2.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+bfscale {z0.h-z1.h}, {z2.h-z3.h}, z8.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+
+// Multiple and single vector, 4 regs
+
+bfscale {z0.s-z3.s}, {z0.s-z3.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z1.h-z4.h}, {z1.h-z4.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfscale {z0.h-z4.h}, {z0.h-z4.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+bfscale {z0.h-z3.h}, {z4.h-z7.h}, z8.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+
+// Multiple vectors, 2 regs
+
+bfscale {z0.s-z1.s}, {z0.s-z1.s}, {z2.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z1.h-z2.h}, {z1.h-z2.h}, {z2.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfscale {z0.h-z2.h}, {z0.h-z4.h}, {z2.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z2.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z28.h-z30.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z29.h-z30.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfscale {z0.h-z1.h}, {z2.h-z3.h}, {z28.h-z29.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+
+// Multiple vectors, 4 regs
+
+bfscale {z0.s-z3.s}, {z0.s-z3.s}, {z4.h-z7.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z1.h-z4.h}, {z1.h-z4.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfscale {z0.h-z4.h}, {z0.h-z4.h}, {z4.h-z7.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z4.s-z7.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z4.h-z8.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z5.h-z8.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfscale {z0.h-z3.h}, {z4.h-z7.h}, {z8.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2/bfscale.s b/llvm/test/MC/AArch64/SME2/bfscale.s
new file mode 100644
index 00000000000000..719d013b235c05
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfscale.s
@@ -0,0 +1,93 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sve-bfscale - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sve-bfscale -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// Multiple and single vector, 2 regs
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, z0.h // 11000001-00100000-10100001-10000000
+// CHECK-INST: bfscale { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x80,0xa1,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c120a180 <unknown>
+
+bfscale {z20.h-z21.h}, {z20.h-z21.h}, z5.h // 11000001-00100101-10100001-10010100
+// CHECK-INST: bfscale { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x94,0xa1,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c125a194 <unknown>
+
+bfscale {z30.h-z31.h}, {z30.h-z31.h}, z15.h // 11000001-00101111-10100001-10011110
+// CHECK-INST: bfscale { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x9e,0xa1,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c12fa19e <unknown>
+
+// Multiple and single vector, 4 regs
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, z0.h // 11000001-00100000-10101001-10000000
+// CHECK-INST: bfscale { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x80,0xa9,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c120a980 <unknown>
+
+bfscale {z20.h-z23.h}, {z20.h-z23.h}, z5.h // 11000001-00100101-10101001-10010100
+// CHECK-INST: bfscale { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x94,0xa9,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c125a994 <unknown>
+
+bfscale {z28.h-z31.h}, {z28.h-z31.h}, z15.h // 11000001-00101111-10101001-10011100
+// CHECK-INST: bfscale { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x9c,0xa9,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c12fa99c <unknown>
+
+// Multiple vectors, 2 regs
+
+bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} // 11000001-00100000-10110001-10000000
+// CHECK-INST: bfscale { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x80,0xb1,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c120b180 <unknown>
+
+bfscale {z20.h-z21.h}, {z20.h-z21.h}, {z20.h-z21.h} // 11000001-00110100-10110001-10010100
+// CHECK-INST: bfscale { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x94,0xb1,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c134b194 <unknown>
+
+bfscale {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h} // 11000001-00111110-10110001-10011110
+// CHECK-INST: bfscale { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0x9e,0xb1,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c13eb19e <unknown>
+
+// Multiple vectors, 4 regs
+
+bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} // 11000001-00100000-10111001-10000000
+// CHECK-INST: bfscale { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x80,0xb9,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c120b980 <unknown>
+
+bfscale {z20.h-z23.h}, {z20.h-z23.h}, {z20.h-z23.h} // 11000001-00110100-10111001-10010100
+// CHECK-INST: bfscale { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x94,0xb9,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c134b994 <unknown>
+
+bfscale {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h} // 11000001-00111100-10111001-10011100
+// CHECK-INST: bfscale { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9c,0xb9,0x3c,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c13cb99c <unknown>
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