[llvm] [NVPTX] Teach NVPTX about predicates (PR #67468)

[Fraser Cormack via llvm-commits]

================
@@ -10,24 +10,42 @@
 //  Describe NVPTX instructions format
 //
 //===----------------------------------------------------------------------===//
-
 // Vector instruction type enum
 class VecInstTypeEnum<bits<4> val> {
   bits<4> Value=val;
 }
+
 def VecNOP : VecInstTypeEnum<0>;
 
-// Generic NVPTX Format
+def pred : PredicateOperand<
+    /*ValueType*/i1,
+    /*OpTypes*/(ops Int1Regs),
+    (ops (i32 /*AlwaysVal*/zero_reg))> {
+  let PrintMethod = "printPredicateOperand";
+  let ParserMatchClass = ?;
----------------
frasercrmck wrote:

I wonder if adding support to the asm parser should be done as part of this. I'd prefer not to add things that break any codegen/parser loop.

https://github.com/llvm/llvm-project/pull/67468