[llvm] [NVPTX] Teach NVPTX about predicates (PR #67468)

[Fraser Cormack via llvm-commits]

================
@@ -10,24 +10,42 @@
 //  Describe NVPTX instructions format
 //
 //===----------------------------------------------------------------------===//
-
 // Vector instruction type enum
 class VecInstTypeEnum<bits<4> val> {
   bits<4> Value=val;
 }
+
 def VecNOP : VecInstTypeEnum<0>;
 
-// Generic NVPTX Format
+def pred : PredicateOperand<
+    /*ValueType*/i1,
+    /*OpTypes*/(ops Int1Regs),
+    (ops (i32 /*AlwaysVal*/zero_reg))> {
+  let PrintMethod = "printPredicateOperand";
+  let ParserMatchClass = ?;
+  let DecoderMethod = ?;
+}
+
+def switch : OperandWithDefaultOps</*ValueType*/i1, /*defaultops*/(ops (i1 0))>;
 
-class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : Instruction {
+// Generic NVPTX Format
+class NVPTXInstBase <dag outs, dag Ins, string asmstr, list<dag>
+pattern, int defaultPreds = 1> : Instruction {
   field bits<14> Inst;
 
   let Namespace = "NVPTX";
   dag OutOperandList = outs;
-  dag InOperandList = ins;
-  let AsmString = asmstr;
+  dag InOperandList = !if(!and(defaultPreds, isPredicable),
+                          !con(Ins, (ins pred:$predicate, switch:$invert_pred)),
+                          Ins);
+
+  let AsmString = !if(!and(defaultPreds, isPredicable),
+                      !strconcat("$predicate ", asmstr),
----------------
frasercrmck wrote:

If we unconditionally print the space, even if the predicate is `NoRegister`, does that mean all asm will be adjusted right by one? Perhaps the space should be printed as part of the predicate operand instead.

https://github.com/llvm/llvm-project/pull/67468