[llvm] [GlobalISel][AArch64] Legalize G_SPLAT_VECTOR (PR #114006)
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 28 23:13:17 PDT 2024
https://github.com/tschuett created https://github.com/llvm/llvm-project/pull/114006
None
>From 18e4b4382e1df9c16aeac38895e79fed8c51cb79 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Tue, 29 Oct 2024 07:09:03 +0100
Subject: [PATCH] [GlobalISel][AArch64] Legalize G_SPLAT_VECTOR
---
.../Target/GlobalISel/SelectionDAGCompat.td | 1 +
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 4 +
.../GlobalISel/legalize-splat-vector.mir | 143 ++++++++++++++++++
3 files changed, 148 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index d1d0c5ff873410..79c07bc2fc9204 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -148,6 +148,7 @@ def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
def : GINodeEquiv<G_EXTRACT_SUBVECTOR, extract_subvector>;
+def : GINodeEquiv<G_SPLAT_VECTOR, splat_vector>;
def : GINodeEquiv<G_FCEIL, fceil>;
def : GINodeEquiv<G_FCOS, fcos>;
def : GINodeEquiv<G_FSIN, fsin>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index dd65dbe594a634..bcfb8370cb7bec 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1316,6 +1316,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarOrEltToNextPow2(0)
.immIdx(0); // Inform verifier imm idx 0 is handled.
+ // TODO: {nxv8s16, s16}
+ getActionDefinitionsBuilder(G_SPLAT_VECTOR)
+ .legalFor(HasSVE, {{nxv4s32, s32}, {nxv2s64, s64}});
+
getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo());
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
new file mode 100644
index 00000000000000..1b9e4132a40751
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
@@ -0,0 +1,143 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -debug -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL
+
+
+---
+name: test_splat_vector_s64
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s64
+ ; CHECK-SELECT: %imm:gpr64sp = COPY $x0
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64
+ ; CHECK-REGBANK: %imm:gpr(s64) = COPY $x0
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s64
+ ; CHECK-LEGAL: %imm:_(s64) = COPY $x0
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ %imm:_(s64) = COPY $x0
+ %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ $z0 = COPY %splat(<vscale x 2 x s64>)
+...
+---
+name: test_splat_vector_s64_const
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s64_const
+ ; CHECK-SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 9
+ ; CHECK-SELECT-NEXT: %imm:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_const
+ ; CHECK-REGBANK: %imm:gpr(s64) = G_CONSTANT i64 9
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_const
+ ; CHECK-LEGAL: %imm:_(s64) = G_CONSTANT i64 9
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ %imm:_(s64) = G_CONSTANT i64 9
+ %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ $z0 = COPY %splat(<vscale x 2 x s64>)
+...
+---
+name: test_splat_vector_s64_fconst
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s64_fconst
+ ; CHECK-SELECT: %imm:fpr64 = FMOVDi 34
+ ; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY %imm
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D [[COPY]]
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_fconst
+ ; CHECK-REGBANK: %imm:fpr(s64) = G_FCONSTANT double 9.000000e+00
+ ; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY %imm(s64)
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[COPY]](s64)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_fconst
+ ; CHECK-LEGAL: %imm:_(s64) = G_FCONSTANT double 9.000000e+00
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
+ %imm:_(s64) = G_FCONSTANT double 9.0
+ %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
+ $z0 = COPY %splat(<vscale x 2 x s64>)
+...
+---
+name: test_splat_vector_s32
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s32
+ ; CHECK-SELECT: %imm:gpr32sp = COPY $w0
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32
+ ; CHECK-REGBANK: %imm:gpr(s32) = COPY $w0
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s32
+ ; CHECK-LEGAL: %imm:_(s32) = COPY $w0
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ %imm:_(s32) = COPY $w0
+ %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ $z0 = COPY %splat(<vscale x 4 x s32>)
+...
+---
+name: test_splat_vector_s32_const
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s32_const
+ ; CHECK-SELECT: %imm:gpr32common = MOVi32imm 9
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_const
+ ; CHECK-REGBANK: %imm:gpr(s32) = G_CONSTANT i32 9
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_const
+ ; CHECK-LEGAL: %imm:_(s32) = G_CONSTANT i32 9
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ %imm:_(s32) = G_CONSTANT i32 9
+ %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ $z0 = COPY %splat(<vscale x 4 x s32>)
+...
+---
+name: test_splat_vector_s32_fconst
+body: |
+ bb.1:
+ ; CHECK-SELECT-LABEL: name: test_splat_vector_s32_fconst
+ ; CHECK-SELECT: %imm:fpr32 = FMOVSi 28
+ ; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY %imm
+ ; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S [[COPY]]
+ ; CHECK-SELECT-NEXT: $z0 = COPY %splat
+ ;
+ ; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_fconst
+ ; CHECK-REGBANK: %imm:fpr(s32) = G_FCONSTANT float 7.000000e+00
+ ; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %imm(s32)
+ ; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[COPY]](s32)
+ ; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ ;
+ ; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_fconst
+ ; CHECK-LEGAL: %imm:_(s32) = G_FCONSTANT float 7.000000e+00
+ ; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ ; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
+ %imm:_(s32) = G_FCONSTANT float 7.0
+ %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
+ $z0 = COPY %splat(<vscale x 4 x s32>)
+...
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