[llvm] [TableGen] Make `!and` short-circuit when either of the operand is zero (PR #113963)

[Rahul Joshi via llvm-commits]

jurahul wrote:

I had that concern as well, but I thought these lhs and rhs expressions are
not side effecting (modulo error checkin). Or do you propose adding short
circuit variants?

On Mon, Oct 28, 2024 at 5:43 PM Paul C. Anagnostopoulos <
***@***.***> wrote:

> !and and !or are bitwise operators that take an arbitrary number of
> arguments. Given that they are not documented to short-circuit, isn't this
> an incompatible change?
>
> (It's been awhile, so my memory may be failing me.)
>
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https://github.com/llvm/llvm-project/pull/113963