[llvm] [TableGen] [NFC] Refine TableGen code to comply with `clang-tidy` checks (PR #113318)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 28 17:26:21 PDT 2024
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/113318
>From 25c6670c6e2d9e1175fea5ea3dccf90281440379 Mon Sep 17 00:00:00 2001
From: Jerry Sun <sunyiran0817 at gmail.com>
Date: Mon, 21 Oct 2024 12:13:29 -0400
Subject: [PATCH 1/2] refine TableGen files to comply with clang-tidy checks
---
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 20 +-
llvm/utils/TableGen/CallingConvEmitter.cpp | 48 ++--
llvm/utils/TableGen/CodeEmitterGen.cpp | 232 +++++++--------
llvm/utils/TableGen/CodeGenMapTable.cpp | 52 ++--
llvm/utils/TableGen/DAGISelEmitter.cpp | 8 +-
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 30 +-
llvm/utils/TableGen/DXILEmitter.cpp | 42 +--
llvm/utils/TableGen/DirectiveEmitter.cpp | 234 +++++++--------
llvm/utils/TableGen/DisassemblerEmitter.cpp | 4 +-
llvm/utils/TableGen/OptionParserEmitter.cpp | 26 +-
llvm/utils/TableGen/OptionRSTEmitter.cpp | 4 +-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 4 +-
llvm/utils/TableGen/SubtargetEmitter.cpp | 266 +++++++++---------
llvm/utils/TableGen/TableGen.cpp | 12 +-
llvm/utils/TableGen/VTEmitter.cpp | 4 +-
15 files changed, 493 insertions(+), 493 deletions(-)
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 6b8ebf96cdf383..fe8a82e6d7e617 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -25,19 +25,19 @@
using namespace llvm;
/// Collect the full set of implied features for a SubtargetFeature.
-static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
+static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
const Record *Rec) {
assert(Rec->isSubClassOf("SubtargetFeature") &&
"Rec is not a SubtargetFeature");
SeenFeats.insert(Rec);
for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
- CollectImpliedFeatures(SeenFeats, Implied);
+ collectImpliedFeatures(SeenFeats, Implied);
}
-static void CheckFeatureTree(const Record *Root) {
+static void checkFeatureTree(const Record *Root) {
std::set<const Record *> SeenFeats;
- CollectImpliedFeatures(SeenFeats, Root);
+ collectImpliedFeatures(SeenFeats, Root);
// Check that each of the mandatory (implied) features which is an
// ExtensionWithMArch is also enabled by default.
@@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
}
}
-static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
// Look through all SubtargetFeature defs with the given FieldName, and
// collect the set of all Values that that FieldName is set to.
- auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+ auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
llvm::StringSet<> Set;
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
if (Rec->getValueAsString("FieldName") == FieldName) {
@@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
<< "#endif\n\n";
const StringSet<> ARMProcFamilyVals =
- gatherSubtargetFeatureFieldValues("ARMProcFamily");
+ GatherSubtargetFeatureFieldValues("ARMProcFamily");
for (const StringRef &Family : ARMProcFamilyVals.keys())
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
@@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_ARCHITECTURE(ENUM)\n"
<< "#endif\n\n";
// This should correspond to instances of the Architecture tablegen class.
- const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+ const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
for (const StringRef &Arch : ARMArchVals.keys())
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
OS << "\n#undef ARM_ARCHITECTURE\n\n";
@@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- CheckFeatureTree(Arch);
+ checkFeatureTree(Arch);
OS << " {\n"
<< " \"" << Name << "\",\n"
@@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
}
static TableGen::Emitter::Opt
- X("gen-arm-target-def", EmitARMTargetDef,
+ X("gen-arm-target-def", emitArmTargetDef,
"Generate the ARM or AArch64 Architecture information header.");
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index fefc407c354a5d..e44b13f0436313 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -34,12 +34,12 @@ class CallingConvEmitter {
public:
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- void EmitCallingConv(const Record *CC, raw_ostream &O);
- void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
- void EmitArgRegisterLists(raw_ostream &O);
+ void emitCallingConv(const Record *CC, raw_ostream &O);
+ void emitAction(const Record *Action, indent Indent, raw_ostream &O);
+ void emitArgRegisterLists(raw_ostream &O);
};
} // End anonymous namespace
@@ -74,16 +74,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
Records.startTimer("Emit full descriptions");
for (const Record *CC : CCs) {
if (!CC->getValueAsBit("Custom")) {
- EmitCallingConv(CC, O);
+ emitCallingConv(CC, O);
}
}
- EmitArgRegisterLists(O);
+ emitArgRegisterLists(O);
O << "\n#endif // CC_REGISTER_LIST\n";
}
-void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
+void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
const ListInit *CCActions = CC->getValueAsListInit("Actions");
Counter = 0;
@@ -106,8 +106,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
<< std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
// Emit all of the actions, in order.
- for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
- const Record *Action = CCActions->getElementAsRecord(i);
+ for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
+ const Record *Action = CCActions->getElementAsRecord(I);
SwiftAction =
llvm::any_of(Action->getSuperClasses(),
[](const std::pair<const Record *, SMRange> &Class) {
@@ -116,23 +116,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
});
O << "\n";
- EmitAction(Action, indent(2), O);
+ emitAction(Action, indent(2), O);
}
O << "\n return true; // CC didn't match.\n";
O << "}\n";
}
-void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
+void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
raw_ostream &O) {
if (Action->isSubClassOf("CCPredicateAction")) {
O << Indent << "if (";
if (Action->isSubClassOf("CCIfType")) {
const ListInit *VTs = Action->getValueAsListInit("VTs");
- for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
- const Record *VT = VTs->getElementAsRecord(i);
- if (i != 0)
+ for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
+ const Record *VT = VTs->getElementAsRecord(I);
+ if (I != 0)
O << " ||\n " << Indent;
O << "LocVT == " << getEnumName(getValueType(VT));
}
@@ -145,7 +145,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
O << ") {\n";
- EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
+ emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
O << Indent << "}\n";
} else {
if (Action->isSubClassOf("CCDelegateTo")) {
@@ -170,8 +170,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
- std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
+ std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
if (SwiftAction)
AssignedSwiftRegsMap[CurrentAction].insert(Name);
else
@@ -229,16 +229,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i)
- O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(RegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
<< "[] = {\n";
O << Indent << " ";
ListSeparator LSS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
@@ -286,8 +286,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< ShadowRegListNumber << "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
@@ -356,7 +356,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
}
-void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
+void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
// Transitively merge all delegated CCs into AssignedRegsMap.
using EntryTy = std::pair<std::string, std::set<std::string>>;
bool Redo;
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 4d356774f98dcc..74c105986104da 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -52,10 +52,10 @@ class CodeEmitterGen {
public:
CodeEmitterGen(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit);
+ int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit);
std::pair<std::string, std::string>
getInstructionCases(const Record *R, const CodeGenTarget &Target);
void addInstructionCasesForEncoding(const Record *R,
@@ -69,10 +69,10 @@ class CodeEmitterGen {
const CodeGenTarget &Target);
void emitInstructionBaseValues(
- raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
+ raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
void
- emitCaseMap(raw_ostream &o,
+ emitCaseMap(raw_ostream &O,
const std::map<std::string, std::vector<std::string>> &CaseMap);
unsigned BitWidth = 0u;
bool UseAPInt = false;
@@ -81,12 +81,12 @@ class CodeEmitterGen {
// If the VarBitInit at position 'bit' matches the specified variable then
// return the variable bit position. Otherwise return -1.
int CodeEmitterGen::getVariableBit(const std::string &VarName,
- const BitsInit *BI, int bit) {
- if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
+ const BitsInit *BI, int Bit) {
+ if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(Bit))) {
if (const VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
if (VI->getName() == VarName)
return VBI->getBitNum();
- } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
+ } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(Bit))) {
if (VI->getName() == VarName)
return 0;
}
@@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
CodeGenInstruction &CGI = Target.getInstruction(R);
// Determine if VarName actually contributes to the Inst encoding.
- int bit = BI->getNumBits() - 1;
+ int Bit = BI->getNumBits() - 1;
// Scan for a bit that this contributed to.
- for (; bit >= 0;) {
- if (getVariableBit(VarName, BI, bit) != -1)
+ for (; Bit >= 0;) {
+ if (getVariableBit(VarName, BI, Bit) != -1)
break;
- --bit;
+ --Bit;
}
// If we found no bits, ignore this value, otherwise emit the call to get the
// operand encoding.
- if (bit < 0)
+ if (Bit < 0)
return true;
// If the operand matches by name, reference according to that
@@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
// Precalculate the number of lits this variable contributes to in the
// operand. If there is a single lit (consecutive range of bits) we can use a
// destructive sequence on APInt that reduces memory allocations.
- int numOperandLits = 0;
- for (int tmpBit = bit; tmpBit >= 0;) {
- int varBit = getVariableBit(VarName, BI, tmpBit);
+ int NumOperandLits = 0;
+ for (int TmpBit = Bit; TmpBit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, TmpBit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --tmpBit;
+ if (VarBit == -1) {
+ --TmpBit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginVarBit = varBit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--tmpBit; tmpBit >= 0;) {
- varBit = getVariableBit(VarName, BI, tmpBit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--TmpBit; TmpBit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, TmpBit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --tmpBit;
+ --TmpBit;
}
- ++numOperandLits;
+ ++NumOperandLits;
}
unsigned BitOffset = -1;
- for (; bit >= 0;) {
- int varBit = getVariableBit(VarName, BI, bit);
+ for (; Bit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, Bit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --bit;
+ if (VarBit == -1) {
+ --Bit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginInstBit = bit;
- int beginVarBit = varBit;
+ int BeginInstBit = Bit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--bit; bit >= 0;) {
- varBit = getVariableBit(VarName, BI, bit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--Bit; Bit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, Bit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --bit;
+ --Bit;
}
- std::string maskStr;
- int opShift;
+ std::string MaskStr;
+ int OpShift;
- unsigned loBit = beginVarBit - N + 1;
- unsigned hiBit = loBit + N;
- unsigned loInstBit = beginInstBit - N + 1;
- BitOffset = loInstBit;
+ unsigned LoBit = BeginVarBit - N + 1;
+ unsigned HiBit = LoBit + N;
+ unsigned LoInstBit = BeginInstBit - N + 1;
+ BitOffset = LoInstBit;
if (UseAPInt) {
- std::string extractStr;
+ std::string ExtractStr;
if (N >= 64) {
- extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
- itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ");\n";
+ ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " +
+ itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ");\n";
} else {
- extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) +
- ", " + itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n";
+ ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) +
+ ", " + itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n";
}
} else {
- uint64_t opMask = ~(uint64_t)0 >> (64 - N);
- opShift = beginVarBit - N + 1;
- opMask <<= opShift;
- maskStr = "UINT64_C(" + utostr(opMask) + ")";
- opShift = beginInstBit - beginVarBit;
-
- if (numOperandLits == 1) {
- Case += " op &= " + maskStr + ";\n";
- if (opShift > 0) {
- Case += " op <<= " + itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " op >>= " + itostr(-opShift) + ";\n";
+ uint64_t OpMask = ~(uint64_t)0 >> (64 - N);
+ OpShift = BeginVarBit - N + 1;
+ OpMask <<= OpShift;
+ MaskStr = "UINT64_C(" + utostr(OpMask) + ")";
+ OpShift = BeginInstBit - BeginVarBit;
+
+ if (NumOperandLits == 1) {
+ Case += " op &= " + MaskStr + ";\n";
+ if (OpShift > 0) {
+ Case += " op <<= " + itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " op >>= " + itostr(-OpShift) + ";\n";
}
Case += " Value |= op;\n";
} else {
- if (opShift > 0) {
- Case += " Value |= (op & " + maskStr + ") << " +
- itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " Value |= (op & " + maskStr + ") >> " +
- itostr(-opShift) + ";\n";
+ if (OpShift > 0) {
+ Case += " Value |= (op & " + MaskStr + ") << " +
+ itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " Value |= (op & " + MaskStr + ") >> " +
+ itostr(-OpShift) + ";\n";
} else {
- Case += " Value |= (op & " + maskStr + ");\n";
+ Case += " Value |= (op & " + MaskStr + ");\n";
}
}
}
@@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
const CodeGenTarget &Target) {
std::string Case, BitOffsetCase;
- auto append = [&](const std::string &S) {
+ auto Append = [&](const std::string &S) {
Case += S;
BitOffsetCase += S;
};
@@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
// Invoke the interface to obtain the HwMode ID controlling the
// EncodingInfo for the current subtarget. This interface will
// mask off irrelevant HwMode IDs.
- append(" unsigned HwMode = "
+ Append(" unsigned HwMode = "
"STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n");
Case += " switch (HwMode) {\n";
Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); "
@@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R,
Case += " Value = InstBitsByHw[opcode];\n";
}
- append(" switch (HwMode) {\n");
- append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
+ Append(" switch (HwMode) {\n");
+ Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
for (auto &[ModeId, Encoding] : EBM) {
- append(" case " + itostr(ModeId) + ": {\n");
+ Append(" case " + itostr(ModeId) + ": {\n");
addInstructionCasesForEncoding(R, Encoding, Target, Case,
BitOffsetCase);
- append(" break;\n");
- append(" }\n");
+ Append(" break;\n");
+ Append(" }\n");
}
- append(" }\n");
+ Append(" }\n");
return std::pair(std::move(Case), std::move(BitOffsetCase));
}
}
@@ -397,13 +397,13 @@ static void emitInstBits(raw_ostream &OS, const APInt &Bits) {
}
void CodeEmitterGen::emitInstructionBaseValues(
- raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
+ raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
const CodeGenTarget &Target, unsigned HwMode) {
const CodeGenHwModes &HWM = Target.getHwModes();
if (HwMode == DefaultMode)
- o << " static const uint64_t InstBits[] = {\n";
+ O << " static const uint64_t InstBits[] = {\n";
else
- o << " static const uint64_t InstBits_"
+ O << " static const uint64_t InstBits_"
<< HWM.getModeName(HwMode, /*IncludeDefault=*/true) << "[] = {\n";
for (const CodeGenInstruction *CGI : NumberedInstructions) {
@@ -411,9 +411,9 @@ void CodeEmitterGen::emitInstructionBaseValues(
if (R->getValueAsString("Namespace") == "TargetOpcode" ||
R->getValueAsBit("isPseudo")) {
- o << " ";
- emitInstBits(o, APInt(BitWidth, 0));
- o << ",\n";
+ O << " ";
+ emitInstBits(O, APInt(BitWidth, 0));
+ O << ",\n";
continue;
}
@@ -427,9 +427,9 @@ void CodeEmitterGen::emitInstructionBaseValues(
// If the HwMode does not match, then Encoding '0'
// should be generated.
APInt Value(BitWidth, 0);
- o << " ";
- emitInstBits(o, Value);
- o << "," << '\t' << "// " << R->getName() << "\n";
+ O << " ";
+ emitInstBits(O, Value);
+ O << "," << '\t' << "// " << R->getName() << "\n";
continue;
}
}
@@ -438,37 +438,37 @@ void CodeEmitterGen::emitInstructionBaseValues(
// Start by filling in fixed values.
APInt Value(BitWidth, 0);
- for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
- if (const auto *B = dyn_cast<BitInit>(BI->getBit(i)); B && B->getValue())
- Value.setBit(i);
+ for (unsigned I = 0, E = BI->getNumBits(); I != E; ++I) {
+ if (const auto *B = dyn_cast<BitInit>(BI->getBit(I)); B && B->getValue())
+ Value.setBit(I);
}
- o << " ";
- emitInstBits(o, Value);
- o << "," << '\t' << "// " << R->getName() << "\n";
+ O << " ";
+ emitInstBits(O, Value);
+ O << "," << '\t' << "// " << R->getName() << "\n";
}
- o << " UINT64_C(0)\n };\n";
+ O << " UINT64_C(0)\n };\n";
}
void CodeEmitterGen::emitCaseMap(
- raw_ostream &o,
+ raw_ostream &O,
const std::map<std::string, std::vector<std::string>> &CaseMap) {
for (const auto &[Case, InstList] : CaseMap) {
bool First = true;
for (const auto &Inst : InstList) {
if (!First)
- o << "\n";
- o << " case " << Inst << ":";
+ O << "\n";
+ O << " case " << Inst << ":";
First = false;
}
- o << " {\n";
- o << Case;
- o << " break;\n"
+ O << " {\n";
+ O << Case;
+ O << " break;\n"
<< " }\n";
}
}
-void CodeEmitterGen::run(raw_ostream &o) {
- emitSourceFileHeader("Machine Code Emitter", o);
+void CodeEmitterGen::run(raw_ostream &O) {
+ emitSourceFileHeader("Machine Code Emitter", O);
CodeGenTarget Target(Records);
@@ -479,7 +479,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
Target.getInstructionsByEnumValue();
if (Target.hasVariableLengthEncodings()) {
- emitVarLenCodeEmitter(Records, o);
+ emitVarLenCodeEmitter(Records, O);
} else {
const CodeGenHwModes &HWM = Target.getHwModes();
// The set of HwModes used by instruction encodings.
@@ -509,31 +509,31 @@ void CodeEmitterGen::run(raw_ostream &o) {
// Emit function declaration
if (UseAPInt) {
- o << "void " << Target.getName()
+ O << "void " << Target.getName()
<< "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
<< " SmallVectorImpl<MCFixup> &Fixups,\n"
<< " APInt &Inst,\n"
<< " APInt &Scratch,\n"
<< " const MCSubtargetInfo &STI) const {\n";
} else {
- o << "uint64_t " << Target.getName();
- o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
+ O << "uint64_t " << Target.getName();
+ O << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
<< " SmallVectorImpl<MCFixup> &Fixups,\n"
<< " const MCSubtargetInfo &STI) const {\n";
}
// Emit instruction base values
- emitInstructionBaseValues(o, NumberedInstructions, Target, DefaultMode);
+ emitInstructionBaseValues(O, NumberedInstructions, Target, DefaultMode);
if (!HwModes.empty()) {
// Emit table for instrs whose encodings are controlled by HwModes.
for (unsigned HwMode : HwModes) {
if (HwMode == DefaultMode)
continue;
- emitInstructionBaseValues(o, NumberedInstructions, Target, HwMode);
+ emitInstructionBaseValues(O, NumberedInstructions, Target, HwMode);
}
// This pointer will be assigned to the HwMode table later.
- o << " const uint64_t *InstBitsByHw;\n";
+ O << " const uint64_t *InstBitsByHw;\n";
}
// Map to accumulate all the cases.
@@ -557,7 +557,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
// Emit initial function code
if (UseAPInt) {
int NumWords = APInt::getNumWords(BitWidth);
- o << " const unsigned opcode = MI.getOpcode();\n"
+ O << " const unsigned opcode = MI.getOpcode();\n"
<< " if (Scratch.getBitWidth() != " << BitWidth << ")\n"
<< " Scratch = Scratch.zext(" << BitWidth << ");\n"
<< " Inst = APInt(" << BitWidth << ", ArrayRef(InstBits + opcode * "
@@ -566,7 +566,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
<< " APInt &op = Scratch;\n"
<< " switch (opcode) {\n";
} else {
- o << " const unsigned opcode = MI.getOpcode();\n"
+ O << " const unsigned opcode = MI.getOpcode();\n"
<< " uint64_t Value = InstBits[opcode];\n"
<< " uint64_t op = 0;\n"
<< " (void)op; // suppress warning\n"
@@ -574,30 +574,30 @@ void CodeEmitterGen::run(raw_ostream &o) {
}
// Emit each case statement
- emitCaseMap(o, CaseMap);
+ emitCaseMap(O, CaseMap);
// Default case: unhandled opcode
- o << " default:\n"
+ O << " default:\n"
<< " std::string msg;\n"
<< " raw_string_ostream Msg(msg);\n"
<< " Msg << \"Not supported instr: \" << MI;\n"
<< " report_fatal_error(Msg.str().c_str());\n"
<< " }\n";
if (UseAPInt)
- o << " Inst = Value;\n";
+ O << " Inst = Value;\n";
else
- o << " return Value;\n";
- o << "}\n\n";
+ O << " return Value;\n";
+ O << "}\n\n";
- o << "#ifdef GET_OPERAND_BIT_OFFSET\n"
+ O << "#ifdef GET_OPERAND_BIT_OFFSET\n"
<< "#undef GET_OPERAND_BIT_OFFSET\n\n"
<< "uint32_t " << Target.getName()
<< "MCCodeEmitter::getOperandBitOffset(const MCInst &MI,\n"
<< " unsigned OpNum,\n"
<< " const MCSubtargetInfo &STI) const {\n"
<< " switch (MI.getOpcode()) {\n";
- emitCaseMap(o, BitOffsetCaseMap);
- o << " }\n"
+ emitCaseMap(O, BitOffsetCaseMap);
+ O << " }\n"
<< " std::string msg;\n"
<< " raw_string_ostream Msg(msg);\n"
<< " Msg << \"Not supported instr[opcode]: \" << MI << \"[\" << OpNum "
diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp
index b599ee149bcd2b..a318c2fa102528 100644
--- a/llvm/utils/TableGen/CodeGenMapTable.cpp
+++ b/llvm/utils/TableGen/CodeGenMapTable.cpp
@@ -258,12 +258,12 @@ bool MapTableEmitter::isKeyColInstr(const Record *CurInstr) {
// Check if the instruction is a KeyCol instruction.
bool MatchFound = true;
- for (unsigned j = 0, endCF = ColFields->size(); (j < endCF) && MatchFound;
- j++) {
+ for (unsigned J = 0, EndCf = ColFields->size(); (J < EndCf) && MatchFound;
+ J++) {
const RecordVal *ColFieldName =
- CurInstr->getValue(ColFields->getElement(j));
+ CurInstr->getValue(ColFields->getElement(J));
std::string CurInstrVal = ColFieldName->getValue()->getAsUnquotedString();
- std::string KeyColValue = KeyCol->getElement(j)->getAsUnquotedString();
+ std::string KeyColValue = KeyCol->getElement(J)->getAsUnquotedString();
MatchFound = CurInstrVal == KeyColValue;
}
return MatchFound;
@@ -318,12 +318,12 @@ const Record *MapTableEmitter::getInstrForColumn(const Record *KeyInstr,
for (const Record *CurInstr : RelatedInstrVec) {
bool MatchFound = true;
- for (unsigned j = 0, endCF = ColFields->size(); (j < endCF) && MatchFound;
- j++) {
- const Init *ColFieldJ = ColFields->getElement(j);
+ for (unsigned J = 0, EndCf = ColFields->size(); (J < EndCf) && MatchFound;
+ J++) {
+ const Init *ColFieldJ = ColFields->getElement(J);
const Init *CurInstrInit = CurInstr->getValue(ColFieldJ)->getValue();
std::string CurInstrVal = CurInstrInit->getAsUnquotedString();
- const Init *ColFieldJVallue = CurValueCol->getElement(j);
+ const Init *ColFieldJVallue = CurValueCol->getElement(J);
MatchFound = CurInstrVal == ColFieldJVallue->getAsUnquotedString();
}
@@ -368,19 +368,19 @@ unsigned MapTableEmitter::emitBinSearchTable(raw_ostream &OS) {
// Number of columns in the table are NumCol+1 because key instructions are
// emitted as first column.
OS << "Table[][" << NumCol + 1 << "] = {\n";
- for (unsigned i = 0; i < TotalNumInstr; i++) {
- const Record *CurInstr = NumberedInstructions[i]->TheDef;
+ for (unsigned I = 0; I < TotalNumInstr; I++) {
+ const Record *CurInstr = NumberedInstructions[I]->TheDef;
ArrayRef<const Record *> ColInstrs = MapTable[CurInstr];
std::string OutStr;
unsigned RelExists = 0;
if (!ColInstrs.empty()) {
- for (unsigned j = 0; j < NumCol; j++) {
- if (ColInstrs[j] != nullptr) {
+ for (unsigned J = 0; J < NumCol; J++) {
+ if (ColInstrs[J] != nullptr) {
RelExists = 1;
OutStr += ", ";
OutStr += Namespace;
OutStr += "::";
- OutStr += ColInstrs[j]->getName();
+ OutStr += ColInstrs[J]->getName();
} else {
OutStr += ", (uint16_t)-1U";
}
@@ -441,20 +441,20 @@ void MapTableEmitter::emitMapFuncBody(raw_ostream &OS, unsigned TableSize) {
emitBinSearch(OS, TableSize);
if (ValueCols.size() > 1) {
- for (unsigned i = 0, e = ValueCols.size(); i < e; i++) {
- const ListInit *ColumnI = ValueCols[i];
+ for (unsigned I = 0, E = ValueCols.size(); I < E; I++) {
+ const ListInit *ColumnI = ValueCols[I];
OS << " if (";
- for (unsigned j = 0, ColSize = ColumnI->size(); j < ColSize; ++j) {
- std::string ColName = ColFields->getElement(j)->getAsUnquotedString();
+ for (unsigned J = 0, ColSize = ColumnI->size(); J < ColSize; ++J) {
+ std::string ColName = ColFields->getElement(J)->getAsUnquotedString();
OS << "in" << ColName;
OS << " == ";
- OS << ColName << "_" << ColumnI->getElement(j)->getAsUnquotedString();
- if (j < ColumnI->size() - 1)
+ OS << ColName << "_" << ColumnI->getElement(J)->getAsUnquotedString();
+ if (J < ColumnI->size() - 1)
OS << " && ";
}
OS << ")\n";
OS << " return " << InstrMapDesc.getName();
- OS << "Table[mid][" << i + 1 << "];\n";
+ OS << "Table[mid][" << I + 1 << "];\n";
}
OS << " return -1;";
} else
@@ -509,8 +509,8 @@ static void emitEnums(raw_ostream &OS, const RecordKeeper &Records) {
std::vector<const ListInit *> ValueCols;
unsigned ListSize = List->size();
- for (unsigned j = 0; j < ListSize; j++) {
- const auto *ListJ = cast<ListInit>(List->getElement(j));
+ for (unsigned J = 0; J < ListSize; J++) {
+ const auto *ListJ = cast<ListInit>(List->getElement(J));
if (ListJ->size() != ColFields->size())
PrintFatalError("Record `" + CurMap->getName() +
@@ -520,10 +520,10 @@ static void emitEnums(raw_ostream &OS, const RecordKeeper &Records) {
ValueCols.push_back(ListJ);
}
- for (unsigned j = 0, endCF = ColFields->size(); j < endCF; j++) {
- for (unsigned k = 0; k < ListSize; k++) {
- std::string ColName = ColFields->getElement(j)->getAsUnquotedString();
- ColFieldValueMap[ColName].push_back((ValueCols[k])->getElement(j));
+ for (unsigned J = 0, EndCf = ColFields->size(); J < EndCf; J++) {
+ for (unsigned K = 0; K < ListSize; K++) {
+ std::string ColName = ColFields->getElement(J)->getAsUnquotedString();
+ ColFieldValueMap[ColName].push_back((ValueCols[K])->getElement(J));
}
}
}
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 2cceb22afdb99b..fcadd59159ee49 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -54,8 +54,8 @@ static unsigned getResultPatternCost(TreePatternNode &P,
if (II.usesCustomInserter)
Cost += 10;
}
- for (unsigned i = 0, e = P.getNumChildren(); i != e; ++i)
- Cost += getResultPatternCost(P.getChild(i), CGP);
+ for (unsigned I = 0, E = P.getNumChildren(); I != E; ++I)
+ Cost += getResultPatternCost(P.getChild(I), CGP);
return Cost;
}
@@ -71,8 +71,8 @@ static unsigned getResultPatternSize(TreePatternNode &P,
if (Op->isSubClassOf("Instruction")) {
Cost += Op->getValueAsInt("CodeSize");
}
- for (unsigned i = 0, e = P.getNumChildren(); i != e; ++i)
- Cost += getResultPatternSize(P.getChild(i), CGP);
+ for (unsigned I = 0, E = P.getNumChildren(); I != E; ++I)
+ Cost += getResultPatternSize(P.getChild(I), CGP);
return Cost;
}
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 537bee55978bd6..a6c0d09f69ba34 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -105,7 +105,7 @@ int DFAPacketizerEmitter::collectAllFuncUnits(
for (const CodeGenProcModel *Model : ProcModels)
ProcItinList.insert(Model->ItinsDef);
- int totalFUs = 0;
+ int TotalFUs = 0;
// Parse functional units for all the itineraries.
for (const Record *Proc : ProcItinList) {
std::vector<const Record *> FUs = Proc->getValueAsListOfDefs("FU");
@@ -123,10 +123,10 @@ int DFAPacketizerEmitter::collectAllFuncUnits(
LLVM_DEBUG(dbgs() << " " << FUs[j]->getName() << ":0x"
<< Twine::utohexstr(FuncResources));
}
- totalFUs += numFUs;
+ TotalFUs += numFUs;
LLVM_DEBUG(dbgs() << "\n");
}
- return totalFUs;
+ return TotalFUs;
}
int DFAPacketizerEmitter::collectAllComboFuncs(
@@ -136,19 +136,19 @@ int DFAPacketizerEmitter::collectAllComboFuncs(
LLVM_DEBUG(dbgs() << "collectAllComboFuncs");
LLVM_DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
- int numCombos = 0;
- for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
- const Record *Func = ComboFuncList[i];
+ int NumCombos = 0;
+ for (unsigned I = 0, N = ComboFuncList.size(); I < N; ++I) {
+ const Record *Func = ComboFuncList[I];
std::vector<const Record *> FUs = Func->getValueAsListOfDefs("CFD");
- LLVM_DEBUG(dbgs() << " CFD:" << i << " (" << FUs.size() << " combo FUs) "
+ LLVM_DEBUG(dbgs() << " CFD:" << I << " (" << FUs.size() << " combo FUs) "
<< Func->getName() << "\n");
// Convert macros to bits for each stage.
- for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
- assert((j < DFA_MAX_RESOURCES) &&
+ for (unsigned J = 0, N = FUs.size(); J < N; ++J) {
+ assert((J < DFA_MAX_RESOURCES) &&
"Exceeded maximum number of DFA resources");
- const Record *FuncData = FUs[j];
+ const Record *FuncData = FUs[J];
const Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
const std::vector<const Record *> FuncList =
FuncData->getValueAsListOfDefs("FuncList");
@@ -165,13 +165,13 @@ int DFAPacketizerEmitter::collectAllComboFuncs(
ComboResources |= FuncResources;
}
ComboBitToBitsMap[ComboBit] = ComboResources;
- numCombos++;
+ NumCombos++;
LLVM_DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
<< Twine::utohexstr(ComboBit) << " = 0x"
<< Twine::utohexstr(ComboResources) << "\n");
}
}
- return numCombos;
+ return NumCombos;
}
ResourceVector
@@ -271,7 +271,7 @@ void DFAPacketizerEmitter::emitForItineraries(
// Given a resource state, return all resource states by applying
// InsnClass.
- auto applyInsnClass = [&](const ResourceVector &InsnClass,
+ auto ApplyInsnClass = [&](const ResourceVector &InsnClass,
NfaStateTy State) -> std::deque<NfaStateTy> {
std::deque<NfaStateTy> V(1, State);
// Apply every stage in the class individually.
@@ -304,7 +304,7 @@ void DFAPacketizerEmitter::emitForItineraries(
// Given a resource state, return a quick (conservative) guess as to whether
// InsnClass can be applied. This is a filter for the more heavyweight
- // applyInsnClass.
+ // ApplyInsnClass.
auto canApplyInsnClass = [](const ResourceVector &InsnClass,
NfaStateTy State) -> bool {
for (NfaStateTy Resources : InsnClass) {
@@ -325,7 +325,7 @@ void DFAPacketizerEmitter::emitForItineraries(
if (!canApplyInsnClass(Resources, State))
continue;
unsigned ResourcesID = UniqueResources.idFor(Resources);
- for (uint64_t NewState : applyInsnClass(Resources, State)) {
+ for (uint64_t NewState : ApplyInsnClass(Resources, State)) {
if (SeenStates.emplace(NewState).second)
Worklist.emplace_back(NewState);
Emitter.addTransition(State, NewState, ResourcesID);
diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp
index 06bf7a0c0a8372..3fadc0ab91e7cb 100644
--- a/llvm/utils/TableGen/DXILEmitter.cpp
+++ b/llvm/utils/TableGen/DXILEmitter.cpp
@@ -49,7 +49,7 @@ struct DXILOperationDesc {
ShaderStages; // shader stages to which this applies, empty for all.
int OverloadParamIndex; // Index of parameter with overload type.
// -1 : no overload types
- SmallVector<StringRef, 4> counters; // counters for this inst.
+ SmallVector<StringRef, 4> Counters; // counters for this inst.
DXILOperationDesc(const Record *);
};
} // end anonymous namespace
@@ -57,7 +57,7 @@ struct DXILOperationDesc {
/// In-place sort TableGen records of class with a field
/// Version dxil_version
/// in the ascending version order.
-static void AscendingSortByVersion(std::vector<const Record *> &Recs) {
+static void ascendingSortByVersion(std::vector<const Record *> &Recs) {
sort(Recs, [](const Record *RecA, const Record *RecB) {
unsigned RecAMaj =
RecA->getValueAsDef("dxil_version")->getValueAsInt("Major");
@@ -98,8 +98,8 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
// the comment before the definition of class LLVMMatchType in
// llvm/IR/Intrinsics.td
OverloadParamIndex = -1; // A sigil meaning none.
- for (unsigned i = 0; i < ParamTypeRecsSize; i++) {
- const Record *TR = ParamTypeRecs[i];
+ for (unsigned I = 0; I < ParamTypeRecsSize; I++) {
+ const Record *TR = ParamTypeRecs[I];
// Track operation parameter indices of any overload types
if (TR->getValueAsInt("isOverload")) {
if (OverloadParamIndex != -1) {
@@ -110,7 +110,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
// Keep the earliest parameter index we see, but if it was the return type
// overwrite it with the first overloaded argument.
if (OverloadParamIndex <= 0)
- OverloadParamIndex = i;
+ OverloadParamIndex = I;
}
OpTypes.emplace_back(TR);
}
@@ -119,7 +119,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
std::vector<const Record *> Recs = R->getValueAsListOfDefs("overloads");
// Sort records in ascending order of DXIL version
- AscendingSortByVersion(Recs);
+ ascendingSortByVersion(Recs);
for (const Record *CR : Recs) {
OverloadRecs.push_back(CR);
@@ -134,7 +134,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
}
// Sort records in ascending order of DXIL version
- AscendingSortByVersion(Recs);
+ ascendingSortByVersion(Recs);
for (const Record *CR : Recs) {
StageRecs.push_back(CR);
@@ -144,7 +144,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
Recs = R->getValueAsListOfDefs("attributes");
// Sort records in ascending order of DXIL version
- AscendingSortByVersion(Recs);
+ ascendingSortByVersion(Recs);
for (const Record *CR : Recs) {
AttrRecs.push_back(CR);
@@ -210,7 +210,7 @@ static std::string getOverloadMaskString(ArrayRef<const Record *> Recs) {
if (Recs.empty()) {
MaskString.append("{{1, 0}, OverloadKind::UNDEFINED}}");
} else {
- for (auto Rec : Recs) {
+ for (const auto *Rec : Recs) {
unsigned Major =
Rec->getValueAsDef("dxil_version")->getValueAsInt("Major");
unsigned Minor =
@@ -256,7 +256,7 @@ static std::string getStageMaskString(ArrayRef<const Record *> Recs) {
"operation must be specified");
}
- for (auto Rec : Recs) {
+ for (const auto *Rec : Recs) {
unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major");
unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor");
MaskString.append(Prefix)
@@ -294,7 +294,7 @@ static std::string getAttributeMaskString(ArrayRef<const Record *> Recs) {
std::string Prefix = "";
MaskString.append("{");
- for (auto Rec : Recs) {
+ for (const auto *Rec : Recs) {
unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major");
unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor");
MaskString.append(Prefix)
@@ -481,21 +481,21 @@ static void emitDXILOperationTableDataStructs(const RecordKeeper &Records,
size_t ShaderKindCount = ShaderKindRecs.size();
uint64_t ShaderKindTySz = PowerOf2Ceil(ShaderKindRecs.size() + 1);
OS << "enum ShaderKind : uint" << ShaderKindTySz << "_t {\n";
- const std::string allStages("all_stages");
- const std::string removed("removed");
- int shiftVal = 1;
- for (auto R : ShaderKindRecs) {
+ const std::string AllStages("all_stages");
+ const std::string Removed("removed");
+ int ShiftVal = 1;
+ for (const auto *R : ShaderKindRecs) {
auto Name = R->getName();
- if (Name.compare(removed) == 0) {
+ if (Name.compare(Removed) == 0) {
OS << " " << Name
<< " = 0, // Pseudo-stage indicating op not supported in any "
"stage\n";
- } else if (Name.compare(allStages) == 0) {
+ } else if (Name.compare(AllStages) == 0) {
OS << " " << Name << " = 0x"
<< utohexstr(((1 << ShaderKindCount) - 1), false, 0)
<< ", // Pseudo-stage indicating op is supported in all stages\n";
- } else if (Name.compare(allStages)) {
- OS << " " << Name << " = 1 << " << std::to_string(shiftVal++) << ",\n";
+ } else if (Name.compare(AllStages)) {
+ OS << " " << Name << " = 1 << " << std::to_string(ShiftVal++) << ",\n";
}
}
OS << "}; // enum ShaderKind\n\n";
@@ -504,7 +504,7 @@ static void emitDXILOperationTableDataStructs(const RecordKeeper &Records,
/// Entry function call that invokes the functionality of this TableGen backend
/// \param Records TableGen records of DXIL Operations defined in DXIL.td
/// \param OS output stream
-static void EmitDXILOperation(const RecordKeeper &Records, raw_ostream &OS) {
+static void emitDxilOperation(const RecordKeeper &Records, raw_ostream &OS) {
OS << "// Generated code, do not edit.\n";
OS << "\n";
// Get all DXIL Ops property records
@@ -536,5 +536,5 @@ static void EmitDXILOperation(const RecordKeeper &Records, raw_ostream &OS) {
OS << "#endif\n\n";
}
-static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation,
+static TableGen::Emitter::Opt X("gen-dxil-operation", emitDxilOperation,
"Generate DXIL operation information");
diff --git a/llvm/utils/TableGen/DirectiveEmitter.cpp b/llvm/utils/TableGen/DirectiveEmitter.cpp
index 9dc29d8262fa2c..fd815f4a31dad8 100644
--- a/llvm/utils/TableGen/DirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/DirectiveEmitter.cpp
@@ -46,7 +46,7 @@ class IfDefScope {
// Generate enum class. Entries are emitted in the order in which they appear
// in the `Records` vector.
-static void GenerateEnumClass(ArrayRef<const Record *> Records, raw_ostream &OS,
+static void generateEnumClass(ArrayRef<const Record *> Records, raw_ostream &OS,
StringRef Enum, StringRef Prefix,
const DirectiveLanguage &DirLang,
bool ExportEnums) {
@@ -79,7 +79,7 @@ static void GenerateEnumClass(ArrayRef<const Record *> Records, raw_ostream &OS,
// Generate enums for values that clauses can take.
// Also generate function declarations for get<Enum>Name(StringRef Str).
-static void GenerateEnumClauseVal(ArrayRef<const Record *> Records,
+static void generateEnumClauseVal(ArrayRef<const Record *> Records,
raw_ostream &OS,
const DirectiveLanguage &DirLang,
std::string &EnumHelperFuncs) {
@@ -121,13 +121,13 @@ static void GenerateEnumClauseVal(ArrayRef<const Record *> Records,
}
}
-static bool HasDuplicateClauses(ArrayRef<const Record *> Clauses,
+static bool hasDuplicateClauses(ArrayRef<const Record *> Clauses,
const Directive &Directive,
StringSet<> &CrtClauses) {
bool HasError = false;
for (const VersionedClause VerClause : Clauses) {
- const auto insRes = CrtClauses.insert(VerClause.getClause().getName());
- if (!insRes.second) {
+ const auto InsRes = CrtClauses.insert(VerClause.getClause().getName());
+ if (!InsRes.second) {
PrintError("Clause " + VerClause.getClause().getRecordName() +
" already defined on directive " + Directive.getRecordName());
HasError = true;
@@ -140,20 +140,20 @@ static bool HasDuplicateClauses(ArrayRef<const Record *> Clauses,
// three allowed list. Also, since required implies allowed, clauses cannot
// appear in both the allowedClauses and requiredClauses lists.
static bool
-HasDuplicateClausesInDirectives(ArrayRef<const Record *> Directives) {
+hasDuplicateClausesInDirectives(ArrayRef<const Record *> Directives) {
bool HasDuplicate = false;
for (const Directive Dir : Directives) {
StringSet<> Clauses;
// Check for duplicates in the three allowed lists.
- if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) ||
- HasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) ||
- HasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) {
+ if (hasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) ||
+ hasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) ||
+ hasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) {
HasDuplicate = true;
}
// Check for duplicate between allowedClauses and required
Clauses.clear();
- if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) ||
- HasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) {
+ if (hasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) ||
+ hasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) {
HasDuplicate = true;
}
if (HasDuplicate)
@@ -173,11 +173,11 @@ bool DirectiveLanguage::HasValidityErrors() const {
return true;
}
- return HasDuplicateClausesInDirectives(getDirectives());
+ return hasDuplicateClausesInDirectives(getDirectives());
}
// Count the maximum number of leaf constituents per construct.
-static size_t GetMaxLeafCount(const DirectiveLanguage &DirLang) {
+static size_t getMaxLeafCount(const DirectiveLanguage &DirLang) {
size_t MaxCount = 0;
for (const Directive D : DirLang.getDirectives())
MaxCount = std::max(MaxCount, D.getLeafConstructs().size());
@@ -186,7 +186,7 @@ static size_t GetMaxLeafCount(const DirectiveLanguage &DirLang) {
// Generate the declaration section for the enumeration in the directive
// language.
-static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
+static void emitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
const auto DirLang = DirectiveLanguage(Records);
if (DirLang.HasValidityErrors())
return;
@@ -214,29 +214,29 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
OS << "\nLLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();\n";
// Emit Directive associations
- std::vector<const Record *> associations;
- copy_if(DirLang.getAssociations(), std::back_inserter(associations),
+ std::vector<const Record *> Associations;
+ copy_if(DirLang.getAssociations(), std::back_inserter(Associations),
// Skip the "special" value
[](const Record *Def) { return Def->getName() != "AS_FromLeaves"; });
- GenerateEnumClass(associations, OS, "Association",
+ generateEnumClass(Associations, OS, "Association",
/*Prefix=*/"", DirLang, /*ExportEnums=*/false);
- GenerateEnumClass(DirLang.getCategories(), OS, "Category", /*Prefix=*/"",
+ generateEnumClass(DirLang.getCategories(), OS, "Category", /*Prefix=*/"",
DirLang, /*ExportEnums=*/false);
// Emit Directive enumeration
- GenerateEnumClass(DirLang.getDirectives(), OS, "Directive",
+ generateEnumClass(DirLang.getDirectives(), OS, "Directive",
DirLang.getDirectivePrefix(), DirLang,
DirLang.hasMakeEnumAvailableInNamespace());
// Emit Clause enumeration
- GenerateEnumClass(DirLang.getClauses(), OS, "Clause",
+ generateEnumClass(DirLang.getClauses(), OS, "Clause",
DirLang.getClausePrefix(), DirLang,
DirLang.hasMakeEnumAvailableInNamespace());
// Emit ClauseVal enumeration
std::string EnumHelperFuncs;
- GenerateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs);
+ generateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs);
// Generic function signatures
OS << "\n";
@@ -259,7 +259,7 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
<< "Clause C, unsigned Version);\n";
OS << "\n";
OS << "constexpr std::size_t getMaxLeafCount() { return "
- << GetMaxLeafCount(DirLang) << "; }\n";
+ << getMaxLeafCount(DirLang) << "; }\n";
OS << "LLVM_ABI Association getDirectiveAssociation(Directive D);\n";
OS << "LLVM_ABI Category getDirectiveCategory(Directive D);\n";
if (EnumHelperFuncs.length() > 0) {
@@ -277,7 +277,7 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) {
}
// Generate function implementation for get<Enum>Name(StringRef Str)
-static void GenerateGetName(ArrayRef<const Record *> Records, raw_ostream &OS,
+static void generateGetName(ArrayRef<const Record *> Records, raw_ostream &OS,
StringRef Enum, const DirectiveLanguage &DirLang,
StringRef Prefix) {
OS << "\n";
@@ -300,11 +300,11 @@ static void GenerateGetName(ArrayRef<const Record *> Records, raw_ostream &OS,
}
// Generate function implementation for get<Enum>Kind(StringRef Str)
-static void GenerateGetKind(ArrayRef<const Record *> Records, raw_ostream &OS,
+static void generateGetKind(ArrayRef<const Record *> Records, raw_ostream &OS,
StringRef Enum, const DirectiveLanguage &DirLang,
StringRef Prefix, bool ImplicitAsUnknown) {
- auto DefaultIt = find_if(
+ const auto *DefaultIt = find_if(
Records, [](const Record *R) { return R->getValueAsBit("isDefault"); });
if (DefaultIt == Records.end()) {
@@ -334,7 +334,7 @@ static void GenerateGetKind(ArrayRef<const Record *> Records, raw_ostream &OS,
}
// Generate function implementation for get<ClauseVal>Kind(StringRef Str)
-static void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang,
+static void generateGetKindClauseVal(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
for (const Clause C : DirLang.getClauses()) {
const auto &ClauseVals = C.getClauseVals();
@@ -389,7 +389,7 @@ static void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang,
}
}
-static void GenerateCaseForVersionedClauses(ArrayRef<const Record *> Clauses,
+static void generateCaseForVersionedClauses(ArrayRef<const Record *> Clauses,
raw_ostream &OS,
StringRef DirectiveName,
const DirectiveLanguage &DirLang,
@@ -406,7 +406,7 @@ static void GenerateCaseForVersionedClauses(ArrayRef<const Record *> Clauses,
}
}
-static std::string GetDirectiveName(const DirectiveLanguage &DirLang,
+static std::string getDirectiveName(const DirectiveLanguage &DirLang,
const Record *Rec) {
Directive Dir(Rec);
return (Twine("llvm::") + DirLang.getCppNamespace() +
@@ -414,12 +414,12 @@ static std::string GetDirectiveName(const DirectiveLanguage &DirLang,
.str();
}
-static std::string GetDirectiveType(const DirectiveLanguage &DirLang) {
+static std::string getDirectiveType(const DirectiveLanguage &DirLang) {
return (Twine("llvm::") + DirLang.getCppNamespace() + "::Directive").str();
}
// Generate the isAllowedClauseForDirective function implementation.
-static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang,
+static void generateIsAllowedClause(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
OS << "\n";
OS << "bool llvm::" << DirLang.getCppNamespace()
@@ -445,16 +445,16 @@ static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang,
StringSet<> Cases;
- GenerateCaseForVersionedClauses(Dir.getAllowedClauses(), OS,
+ generateCaseForVersionedClauses(Dir.getAllowedClauses(), OS,
Dir.getName(), DirLang, Cases);
- GenerateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS,
+ generateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS,
Dir.getName(), DirLang, Cases);
- GenerateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS,
+ generateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS,
Dir.getName(), DirLang, Cases);
- GenerateCaseForVersionedClauses(Dir.getRequiredClauses(), OS,
+ generateCaseForVersionedClauses(Dir.getRequiredClauses(), OS,
Dir.getName(), DirLang, Cases);
OS << " default:\n";
@@ -470,7 +470,7 @@ static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang,
OS << "}\n"; // End of function isAllowedClauseForDirective
}
-static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
+static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
StringRef TableName) {
// The leaf constructs are emitted in a form of a 2D table, where each
// row corresponds to a directive (and there is a row for each directive).
@@ -498,7 +498,7 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
DirId.insert(std::make_pair(Rec, Idx));
using LeafList = std::vector<int>;
- int MaxLeafCount = GetMaxLeafCount(DirLang);
+ int MaxLeafCount = getMaxLeafCount(DirLang);
// The initial leaf table, rows order is same as directive order.
std::vector<LeafList> LeafTable(Directives.size());
@@ -560,19 +560,19 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
// type is `int` (by default). The code above uses `int` to store directive
// ids, so make sure that we catch it when something changes in the
// underlying type.
- std::string DirectiveType = GetDirectiveType(DirLang);
+ std::string DirectiveType = getDirectiveType(DirLang);
OS << "\nstatic_assert(sizeof(" << DirectiveType << ") == sizeof(int));\n";
OS << "[[maybe_unused]] static const " << DirectiveType << ' ' << TableName
<< "[][" << MaxLeafCount + 2 << "] = {\n";
for (size_t I = 0, E = Directives.size(); I != E; ++I) {
auto &Leaves = LeafTable[Ordering[I]];
- OS << " {" << GetDirectiveName(DirLang, Directives[Leaves[0]]);
+ OS << " {" << getDirectiveName(DirLang, Directives[Leaves[0]]);
OS << ", static_cast<" << DirectiveType << ">(" << Leaves[1] << "),";
for (size_t I = 2, E = Leaves.size(); I != E; ++I) {
int Idx = Leaves[I];
if (Idx >= 0)
- OS << ' ' << GetDirectiveName(DirLang, Directives[Leaves[I]]) << ',';
+ OS << ' ' << getDirectiveName(DirLang, Directives[Leaves[I]]) << ',';
else
OS << " static_cast<" << DirectiveType << ">(-1),";
}
@@ -600,7 +600,7 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
OS << "\n};\n";
}
-static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
+static void generateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
enum struct Association {
None = 0, // None should be the smallest value.
@@ -613,10 +613,10 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
Invalid,
};
- ArrayRef<const Record *> associations = DirLang.getAssociations();
+ ArrayRef<const Record *> Associations = DirLang.getAssociations();
- auto getAssocValue = [](StringRef name) -> Association {
- return StringSwitch<Association>(name)
+ auto GetAssocValue = [](StringRef Name) -> Association {
+ return StringSwitch<Association>(Name)
.Case("AS_Block", Association::Block)
.Case("AS_Declaration", Association::Declaration)
.Case("AS_Delimited", Association::Delimited)
@@ -627,24 +627,24 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
.Default(Association::Invalid);
};
- auto getAssocName = [&](Association A) -> StringRef {
+ auto GetAssocName = [&](Association A) -> StringRef {
if (A != Association::Invalid && A != Association::FromLeaves) {
- auto F = find_if(associations, [&](const Record *R) {
- return getAssocValue(R->getName()) == A;
+ const auto *F = find_if(Associations, [&](const Record *R) {
+ return GetAssocValue(R->getName()) == A;
});
- if (F != associations.end())
+ if (F != Associations.end())
return (*F)->getValueAsString("name"); // enum name
}
llvm_unreachable("Unexpected association value");
};
- auto errorPrefixFor = [&](Directive D) -> std::string {
+ auto ErrorPrefixFor = [&](Directive D) -> std::string {
return (Twine("Directive '") + D.getName() + "' in namespace '" +
DirLang.getCppNamespace() + "' ")
.str();
};
- auto reduce = [&](Association A, Association B) -> Association {
+ auto Reduce = [&](Association A, Association B) -> Association {
if (A > B)
std::swap(A, B);
@@ -663,14 +663,14 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
DenseMap<const Record *, Association> AsMap;
- auto compAssocImpl = [&](const Record *R, auto &&Self) -> Association {
+ auto CompAssocImpl = [&](const Record *R, auto &&Self) -> Association {
if (auto F = AsMap.find(R); F != AsMap.end())
return F->second;
Directive D(R);
- Association AS = getAssocValue(D.getAssociation()->getName());
+ Association AS = GetAssocValue(D.getAssociation()->getName());
if (AS == Association::Invalid) {
- PrintFatalError(errorPrefixFor(D) +
+ PrintFatalError(ErrorPrefixFor(D) +
"has an unrecognized value for association: '" +
D.getAssociation()->getName() + "'");
}
@@ -679,22 +679,22 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
return AS;
}
// Compute the association from leaf constructs.
- std::vector<const Record *> leaves = D.getLeafConstructs();
- if (leaves.empty()) {
+ std::vector<const Record *> Leaves = D.getLeafConstructs();
+ if (Leaves.empty()) {
errs() << D.getName() << '\n';
- PrintFatalError(errorPrefixFor(D) +
+ PrintFatalError(ErrorPrefixFor(D) +
"requests association to be computed from leaves, "
"but it has no leaves");
}
- Association Result = Self(leaves[0], Self);
- for (int I = 1, E = leaves.size(); I < E; ++I) {
- Association A = Self(leaves[I], Self);
- Association R = reduce(Result, A);
+ Association Result = Self(Leaves[0], Self);
+ for (int I = 1, E = Leaves.size(); I < E; ++I) {
+ Association A = Self(Leaves[I], Self);
+ Association R = Reduce(Result, A);
if (R == Association::Invalid) {
- PrintFatalError(errorPrefixFor(D) +
+ PrintFatalError(ErrorPrefixFor(D) +
"has leaves with incompatible association values: " +
- getAssocName(A) + " and " + getAssocName(R));
+ GetAssocName(A) + " and " + GetAssocName(R));
}
Result = R;
}
@@ -706,11 +706,11 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
};
for (const Record *R : DirLang.getDirectives())
- compAssocImpl(R, compAssocImpl); // Updates AsMap.
+ CompAssocImpl(R, CompAssocImpl); // Updates AsMap.
OS << '\n';
- auto getQualifiedName = [&](StringRef Formatted) -> std::string {
+ auto GetQualifiedName = [&](StringRef Formatted) -> std::string {
return (Twine("llvm::") + DirLang.getCppNamespace() +
"::Directive::" + DirLang.getDirectivePrefix() + Formatted)
.str();
@@ -727,9 +727,9 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
for (const Record *R : DirLang.getDirectives()) {
if (auto F = AsMap.find(R); F != AsMap.end()) {
Directive Dir(R);
- OS << " case " << getQualifiedName(Dir.getFormattedName()) << ":\n";
+ OS << " case " << GetQualifiedName(Dir.getFormattedName()) << ":\n";
OS << " return " << AssociationTypeName
- << "::" << getAssocName(F->second) << ";\n";
+ << "::" << GetAssocName(F->second) << ";\n";
}
}
OS << " } // switch (Dir)\n";
@@ -737,7 +737,7 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang,
OS << "}\n";
}
-static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang,
+static void generateGetDirectiveCategory(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
std::string LangNamespace = "llvm::" + DirLang.getCppNamespace().str();
std::string CategoryTypeName = LangNamespace + "::Category";
@@ -745,12 +745,12 @@ static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang,
OS << '\n';
OS << CategoryTypeName << ' ' << LangNamespace << "::getDirectiveCategory("
- << GetDirectiveType(DirLang) << " Dir) {\n";
+ << getDirectiveType(DirLang) << " Dir) {\n";
OS << " switch (Dir) {\n";
for (const Record *R : DirLang.getDirectives()) {
Directive D(R);
- OS << " case " << GetDirectiveName(DirLang, R) << ":\n";
+ OS << " case " << getDirectiveName(DirLang, R) << ":\n";
OS << " return " << CategoryNamespace
<< D.getCategory()->getValueAsString("name") << ";\n";
}
@@ -760,7 +760,7 @@ static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang,
}
// Generate a simple enum set with the give clauses.
-static void GenerateClauseSet(ArrayRef<const Record *> Clauses, raw_ostream &OS,
+static void generateClauseSet(ArrayRef<const Record *> Clauses, raw_ostream &OS,
StringRef ClauseSetPrefix, const Directive &Dir,
const DirectiveLanguage &DirLang) {
@@ -778,7 +778,7 @@ static void GenerateClauseSet(ArrayRef<const Record *> Clauses, raw_ostream &OS,
}
// Generate an enum set for the 4 kinds of clauses linked to a directive.
-static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang,
+static void generateDirectiveClauseSets(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_SETS", OS);
@@ -796,13 +796,13 @@ static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang,
OS << "\n";
OS << " // Sets for " << Dir.getName() << "\n";
- GenerateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir,
+ generateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir,
DirLang);
- GenerateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_",
+ generateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_",
Dir, DirLang);
- GenerateClauseSet(Dir.getAllowedExclusiveClauses(), OS,
+ generateClauseSet(Dir.getAllowedExclusiveClauses(), OS,
"allowedExclusiveClauses_", Dir, DirLang);
- GenerateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir,
+ generateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir,
DirLang);
}
@@ -816,7 +816,7 @@ static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang,
// Generate a map of directive (key) with DirectiveClauses struct as values.
// The struct holds the 4 sets of enumeration for the 4 kinds of clauses
// allowances (allowed, allowed once, allowed exclusive and required).
-static void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang,
+static void generateDirectiveClauseMap(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_MAP", OS);
@@ -850,7 +850,7 @@ static void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang,
// If the clause does not hold a value, an EMPTY_CLASS is used.
// If the clause class is generic then a WRAPPER_CLASS is used. When the value
// is optional, the value class is wrapped into a std::optional.
-static void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang,
+static void generateFlangClauseParserClass(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES", OS);
@@ -877,7 +877,7 @@ static void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang,
}
// Generate a list of the different clause classes for Flang.
-static void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang,
+static void generateFlangClauseParserClassList(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES_LIST", OS);
@@ -890,7 +890,7 @@ static void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang,
}
// Generate dump node list for the clauses holding a generic class name.
-static void GenerateFlangClauseDump(const DirectiveLanguage &DirLang,
+static void generateFlangClauseDump(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_DUMP_PARSE_TREE_CLAUSES", OS);
@@ -904,7 +904,7 @@ static void GenerateFlangClauseDump(const DirectiveLanguage &DirLang,
// Generate Unparse functions for clauses classes in the Flang parse-tree
// If the clause is a non-generic class, no entry is generated.
-static void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang,
+static void generateFlangClauseUnparse(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_CLAUSE_UNPARSE", OS);
@@ -955,7 +955,7 @@ static void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang,
}
// Generate check in the Enter functions for clauses classes.
-static void GenerateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang,
+static void generateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_CLAUSE_CHECK_ENTER", OS);
@@ -969,7 +969,7 @@ static void GenerateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang,
// Generate the mapping for clauses between the parser class and the
// corresponding clause Kind
-static void GenerateFlangClauseParserKindMap(const DirectiveLanguage &DirLang,
+static void generateFlangClauseParserKindMap(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_KIND_MAP", OS);
@@ -996,7 +996,7 @@ static bool compareClauseName(const Record *R1, const Record *R2) {
}
// Generate the parser for the clauses.
-static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang,
+static void generateFlangClausesParser(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
std::vector<const Record *> Clauses = DirLang.getClauses();
// Sort clauses in reverse alphabetical order so with clauses with same
@@ -1004,8 +1004,8 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang,
sort(Clauses, compareClauseName);
IfDefScope Scope("GEN_FLANG_CLAUSES_PARSER", OS);
OS << "\n";
- unsigned index = 0;
- unsigned lastClauseIndex = Clauses.size() - 1;
+ unsigned Index = 0;
+ unsigned LastClauseIndex = Clauses.size() - 1;
OS << "TYPE_PARSER(\n";
for (const Clause Clause : Clauses) {
if (Clause.getAliases().empty()) {
@@ -1013,8 +1013,8 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang,
} else {
OS << " ("
<< "\"" << Clause.getName() << "\"_tok";
- for (StringRef alias : Clause.getAliases()) {
- OS << " || \"" << alias << "\"_tok";
+ for (StringRef Alias : Clause.getAliases()) {
+ OS << " || \"" << Alias << "\"_tok";
}
OS << ")";
}
@@ -1024,10 +1024,10 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang,
<< "::" << Clause.getFormattedParserClassName() << ">(";
if (Clause.getFlangClass().empty()) {
OS << "))";
- if (index != lastClauseIndex)
+ if (Index != LastClauseIndex)
OS << " ||";
OS << "\n";
- ++index;
+ ++Index;
continue;
}
@@ -1064,38 +1064,38 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang,
if (Clause.isValueOptional()) // close maybe(.
OS << ")";
OS << "))";
- if (index != lastClauseIndex)
+ if (Index != LastClauseIndex)
OS << " ||";
OS << "\n";
- ++index;
+ ++Index;
}
OS << ")\n";
}
// Generate the implementation section for the enumeration in the directive
// language
-static void EmitDirectivesFlangImpl(const DirectiveLanguage &DirLang,
+static void emitDirectivesFlangImpl(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
- GenerateDirectiveClauseSets(DirLang, OS);
+ generateDirectiveClauseSets(DirLang, OS);
- GenerateDirectiveClauseMap(DirLang, OS);
+ generateDirectiveClauseMap(DirLang, OS);
- GenerateFlangClauseParserClass(DirLang, OS);
+ generateFlangClauseParserClass(DirLang, OS);
- GenerateFlangClauseParserClassList(DirLang, OS);
+ generateFlangClauseParserClassList(DirLang, OS);
- GenerateFlangClauseDump(DirLang, OS);
+ generateFlangClauseDump(DirLang, OS);
- GenerateFlangClauseUnparse(DirLang, OS);
+ generateFlangClauseUnparse(DirLang, OS);
- GenerateFlangClauseCheckPrototypes(DirLang, OS);
+ generateFlangClauseCheckPrototypes(DirLang, OS);
- GenerateFlangClauseParserKindMap(DirLang, OS);
+ generateFlangClauseParserKindMap(DirLang, OS);
- GenerateFlangClausesParser(DirLang, OS);
+ generateFlangClausesParser(DirLang, OS);
}
-static void GenerateClauseClassMacro(const DirectiveLanguage &DirLang,
+static void generateClauseClassMacro(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
// Generate macros style information for legacy code in clang
IfDefScope Scope("GEN_CLANG_CLAUSE_CLASS", OS);
@@ -1163,63 +1163,63 @@ static void GenerateClauseClassMacro(const DirectiveLanguage &DirLang,
// Generate the implemenation for the enumeration in the directive
// language. This code can be included in library.
-void EmitDirectivesBasicImpl(const DirectiveLanguage &DirLang,
+void emitDirectivesBasicImpl(const DirectiveLanguage &DirLang,
raw_ostream &OS) {
IfDefScope Scope("GEN_DIRECTIVES_IMPL", OS);
OS << "\n#include \"llvm/Support/ErrorHandling.h\"\n";
// getDirectiveKind(StringRef Str)
- GenerateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang,
+ generateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang,
DirLang.getDirectivePrefix(), /*ImplicitAsUnknown=*/false);
// getDirectiveName(Directive Kind)
- GenerateGetName(DirLang.getDirectives(), OS, "Directive", DirLang,
+ generateGetName(DirLang.getDirectives(), OS, "Directive", DirLang,
DirLang.getDirectivePrefix());
// getClauseKind(StringRef Str)
- GenerateGetKind(DirLang.getClauses(), OS, "Clause", DirLang,
+ generateGetKind(DirLang.getClauses(), OS, "Clause", DirLang,
DirLang.getClausePrefix(),
/*ImplicitAsUnknown=*/true);
// getClauseName(Clause Kind)
- GenerateGetName(DirLang.getClauses(), OS, "Clause", DirLang,
+ generateGetName(DirLang.getClauses(), OS, "Clause", DirLang,
DirLang.getClausePrefix());
// get<ClauseVal>Kind(StringRef Str)
- GenerateGetKindClauseVal(DirLang, OS);
+ generateGetKindClauseVal(DirLang, OS);
// isAllowedClauseForDirective(Directive D, Clause C, unsigned Version)
- GenerateIsAllowedClause(DirLang, OS);
+ generateIsAllowedClause(DirLang, OS);
// getDirectiveAssociation(Directive D)
- GenerateGetDirectiveAssociation(DirLang, OS);
+ generateGetDirectiveAssociation(DirLang, OS);
// getDirectiveCategory(Directive D)
- GenerateGetDirectiveCategory(DirLang, OS);
+ generateGetDirectiveCategory(DirLang, OS);
// Leaf table for getLeafConstructs, etc.
- EmitLeafTable(DirLang, OS, "LeafConstructTable");
+ emitLeafTable(DirLang, OS, "LeafConstructTable");
}
// Generate the implemenation section for the enumeration in the directive
// language.
-static void EmitDirectivesImpl(const RecordKeeper &Records, raw_ostream &OS) {
+static void emitDirectivesImpl(const RecordKeeper &Records, raw_ostream &OS) {
const auto DirLang = DirectiveLanguage(Records);
if (DirLang.HasValidityErrors())
return;
- EmitDirectivesFlangImpl(DirLang, OS);
+ emitDirectivesFlangImpl(DirLang, OS);
- GenerateClauseClassMacro(DirLang, OS);
+ generateClauseClassMacro(DirLang, OS);
- EmitDirectivesBasicImpl(DirLang, OS);
+ emitDirectivesBasicImpl(DirLang, OS);
}
static TableGen::Emitter::Opt
- X("gen-directive-decl", EmitDirectivesDecl,
+ X("gen-directive-decl", emitDirectivesDecl,
"Generate directive related declaration code (header file)");
static TableGen::Emitter::Opt
- Y("gen-directive-impl", EmitDirectivesImpl,
+ Y("gen-directive-impl", emitDirectivesImpl,
"Generate directive related implementation code");
diff --git a/llvm/utils/TableGen/DisassemblerEmitter.cpp b/llvm/utils/TableGen/DisassemblerEmitter.cpp
index eb15392272a3f3..70d835e699ffef 100644
--- a/llvm/utils/TableGen/DisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/DisassemblerEmitter.cpp
@@ -95,7 +95,7 @@ using namespace llvm::X86Disassembler;
/// X86RecognizableInstr.cpp contains the implementation for a single
/// instruction.
-static void EmitDisassembler(const RecordKeeper &Records, raw_ostream &OS) {
+static void emitDisassembler(const RecordKeeper &Records, raw_ostream &OS) {
const CodeGenTarget Target(Records);
emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS);
@@ -132,5 +132,5 @@ static void EmitDisassembler(const RecordKeeper &Records, raw_ostream &OS) {
cl::OptionCategory DisassemblerEmitterCat("Options for -gen-disassembler");
-static TableGen::Emitter::Opt X("gen-disassembler", EmitDisassembler,
+static TableGen::Emitter::Opt X("gen-disassembler", emitDisassembler,
"Generate disassembler");
diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp
index 424cf16e719d5d..e3c29ba232569f 100644
--- a/llvm/utils/TableGen/OptionParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptionParserEmitter.cpp
@@ -27,7 +27,7 @@ static std::string getOptionName(const Record &R) {
return std::string(R.getValueAsString("EnumName"));
}
-static raw_ostream &write_cstring(raw_ostream &OS, llvm::StringRef Str) {
+static raw_ostream &writeCstring(raw_ostream &OS, llvm::StringRef Str) {
OS << '"';
OS.write_escaped(Str);
OS << '"';
@@ -118,7 +118,7 @@ struct SimpleEnumValueTable {
OS << "static const SimpleEnumValue " << ValueTableName << "[] = {\n";
for (unsigned I = 0, E = Values.size(); I != E; ++I) {
OS << "{";
- write_cstring(OS, Values[I]);
+ writeCstring(OS, Values[I]);
OS << ",";
OS << "static_cast<unsigned>(";
emitScopedNormalizedValue(OS, NormalizedValues[I]);
@@ -191,7 +191,7 @@ static MarshallingInfo createMarshallingInfo(const Record &R) {
return Ret;
}
-static void EmitHelpTextsForVariants(
+static void emitHelpTextsForVariants(
raw_ostream &OS, std::vector<std::pair<std::vector<std::string>, StringRef>>
HelpTextsForVariants) {
// OptTable must be constexpr so it uses std::arrays with these capacities.
@@ -236,7 +236,7 @@ static void EmitHelpTextsForVariants(
OS << "}}, ";
if (Help.size())
- write_cstring(OS, Help);
+ writeCstring(OS, Help);
else
OS << "nullptr";
OS << ")";
@@ -250,7 +250,7 @@ static void EmitHelpTextsForVariants(
/// OptionParserEmitter - This tablegen backend takes an input .td file
/// describing a list of options and emits a data structure for parsing and
/// working with those options when given an input command line.
-static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
+static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
// Get the option groups and options.
ArrayRef<const Record *> Groups =
Records.getAllDerivedDefinitions("OptionGroup");
@@ -364,12 +364,12 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
if (!isa<UnsetInit>(R.getValueInit("HelpText"))) {
OS << ",\n";
OS << " ";
- write_cstring(OS, R.getValueAsString("HelpText"));
+ writeCstring(OS, R.getValueAsString("HelpText"));
} else
OS << ", nullptr";
// Not using Visibility specific text for group help.
- EmitHelpTextsForVariants(OS, {});
+ emitHelpTextsForVariants(OS, {});
// The option meta-variable name (unused).
OS << ", nullptr";
@@ -388,7 +388,7 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
OS << Prefixes[PrefixKeyT(RPrefixes.begin(), RPrefixes.end())] << ", ";
// The option prefixed name.
- write_cstring(OS, getOptionPrefixedName(R));
+ writeCstring(OS, getOptionPrefixedName(R));
// The option identifier name.
OS << ", " << getOptionName(R);
@@ -465,7 +465,7 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
if (!isa<UnsetInit>(R.getValueInit("HelpText"))) {
OS << ",\n";
OS << " ";
- write_cstring(OS, R.getValueAsString("HelpText"));
+ writeCstring(OS, R.getValueAsString("HelpText"));
} else
OS << ", nullptr";
@@ -483,19 +483,19 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
HelpTextsForVariants.push_back(std::make_pair(
VisibilityNames, VisibilityHelp->getValueAsString("Text")));
}
- EmitHelpTextsForVariants(OS, HelpTextsForVariants);
+ emitHelpTextsForVariants(OS, HelpTextsForVariants);
// The option meta-variable name.
OS << ", ";
if (!isa<UnsetInit>(R.getValueInit("MetaVarName")))
- write_cstring(OS, R.getValueAsString("MetaVarName"));
+ writeCstring(OS, R.getValueAsString("MetaVarName"));
else
OS << "nullptr";
// The option Values. Used for shell autocompletion.
OS << ", ";
if (!isa<UnsetInit>(R.getValueInit("Values")))
- write_cstring(OS, R.getValueAsString("Values"));
+ writeCstring(OS, R.getValueAsString("Values"));
else if (!isa<UnsetInit>(R.getValueInit("ValuesCode"))) {
OS << getOptionName(R) << "_Values";
} else
@@ -572,5 +572,5 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
OS << "\n";
}
-static TableGen::Emitter::Opt X("gen-opt-parser-defs", EmitOptionParser,
+static TableGen::Emitter::Opt X("gen-opt-parser-defs", emitOptionParser,
"Generate option definitions");
diff --git a/llvm/utils/TableGen/OptionRSTEmitter.cpp b/llvm/utils/TableGen/OptionRSTEmitter.cpp
index 1b4c4cad4f0a45..6eac10e1831f02 100644
--- a/llvm/utils/TableGen/OptionRSTEmitter.cpp
+++ b/llvm/utils/TableGen/OptionRSTEmitter.cpp
@@ -16,7 +16,7 @@ using namespace llvm;
/// This tablegen backend takes an input .td file describing a list of options
/// and emits a RST man page.
-static void EmitOptionRST(const RecordKeeper &Records, raw_ostream &OS) {
+static void emitOptionRst(const RecordKeeper &Records, raw_ostream &OS) {
llvm::StringMap<std::vector<const Record *>> OptionsByGroup;
// Get the options.
@@ -96,5 +96,5 @@ static void EmitOptionRST(const RecordKeeper &Records, raw_ostream &OS) {
}
}
-static TableGen::Emitter::Opt X("gen-opt-rst", EmitOptionRST,
+static TableGen::Emitter::Opt X("gen-opt-rst", emitOptionRst,
"Generate option RST");
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 23496a37d5ea1c..39211aab6f2d1e 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -244,13 +244,13 @@ static void emitRISCVExtensionBitmask(const RecordKeeper &RK, raw_ostream &OS) {
OS << "#endif\n";
}
-static void EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitRiscvTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
emitRISCVExtensions(RK, OS);
emitRISCVProfiles(RK, OS);
emitRISCVProcs(RK, OS);
emitRISCVExtensionBitmask(RK, OS);
}
-static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
+static TableGen::Emitter::Opt X("gen-riscv-target-def", emitRiscvTargetDef,
"Generate the list of CPUs and extensions for "
"RISC-V");
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 17b84d06fe8573..02c799cb6f1471 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -87,65 +87,65 @@ class SubtargetEmitter {
CodeGenSchedModels &SchedModels;
std::string Target;
- FeatureMapTy Enumeration(raw_ostream &OS);
- void EmitSubtargetInfoMacroCalls(raw_ostream &OS);
- unsigned FeatureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
- unsigned CPUKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
- void FormItineraryStageString(const std::string &Names,
+ FeatureMapTy enumeration(raw_ostream &OS);
+ void emitSubtargetInfoMacroCalls(raw_ostream &OS);
+ unsigned featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
+ unsigned cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);
+ void formItineraryStageString(const std::string &Names,
const Record *ItinData, std::string &ItinString,
unsigned &NStages);
- void FormItineraryOperandCycleString(const Record *ItinData,
+ void formItineraryOperandCycleString(const Record *ItinData,
std::string &ItinString,
unsigned &NOperandCycles);
- void FormItineraryBypassString(const std::string &Names,
+ void formItineraryBypassString(const std::string &Names,
const Record *ItinData,
std::string &ItinString,
unsigned NOperandCycles);
- void EmitStageAndOperandCycleData(
+ void emitStageAndOperandCycleData(
raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);
- void EmitItineraries(raw_ostream &OS,
+ void emitItineraries(raw_ostream &OS,
std::vector<std::vector<InstrItinerary>> &ProcItinLists);
- unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
+ unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel,
raw_ostream &OS);
- void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
+ void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
raw_ostream &OS);
- void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
+ void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
raw_ostream &OS);
- void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
+ void emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
char Separator);
- void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
+ void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
raw_ostream &OS);
- void EmitProcessorResources(const CodeGenProcModel &ProcModel,
+ void emitProcessorResources(const CodeGenProcModel &ProcModel,
raw_ostream &OS);
- const Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
+ const Record *findWriteResources(const CodeGenSchedRW &SchedWrite,
const CodeGenProcModel &ProcModel);
- const Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
+ const Record *findReadAdvance(const CodeGenSchedRW &SchedRead,
const CodeGenProcModel &ProcModel);
- void ExpandProcResources(ConstRecVec &PRVec,
+ void expandProcResources(ConstRecVec &PRVec,
std::vector<int64_t> &ReleaseAtCycles,
std::vector<int64_t> &AcquireAtCycles,
const CodeGenProcModel &ProcModel);
- void GenSchedClassTables(const CodeGenProcModel &ProcModel,
+ void genSchedClassTables(const CodeGenProcModel &ProcModel,
SchedClassTables &SchedTables);
- void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
- void EmitProcessorModels(raw_ostream &OS);
- void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
+ void emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
+ void emitProcessorModels(raw_ostream &OS);
+ void emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
void emitSchedModelHelpersImpl(raw_ostream &OS,
bool OnlyExpandMCInstPredicates = false);
void emitGenMCSubtargetInfo(raw_ostream &OS);
- void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
+ void emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS);
- void EmitSchedModel(raw_ostream &OS);
+ void emitSchedModel(raw_ostream &OS);
void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS);
- void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
- void ParseFeaturesFunction(raw_ostream &OS);
+ void emitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
+ void parseFeaturesFunction(raw_ostream &OS);
public:
SubtargetEmitter(const RecordKeeper &R)
: TGT(R), Records(R), SchedModels(TGT.getSchedModels()),
Target(TGT.getName()) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
};
} // end anonymous namespace
@@ -153,7 +153,7 @@ class SubtargetEmitter {
//
// Enumeration - Emit the specified class as an enumeration.
//
-FeatureMapTy SubtargetEmitter::Enumeration(raw_ostream &OS) {
+FeatureMapTy SubtargetEmitter::enumeration(raw_ostream &OS) {
ArrayRef<const Record *> DefList =
Records.getAllDerivedDefinitions("SubtargetFeature");
@@ -171,15 +171,15 @@ FeatureMapTy SubtargetEmitter::Enumeration(raw_ostream &OS) {
FeatureMapTy FeatureMap;
// For each record
- for (unsigned i = 0; i < N; ++i) {
+ for (unsigned I = 0; I < N; ++I) {
// Next record
- const Record *Def = DefList[i];
+ const Record *Def = DefList[I];
// Get and emit name
- OS << " " << Def->getName() << " = " << i << ",\n";
+ OS << " " << Def->getName() << " = " << I << ",\n";
// Save the index for this feature.
- FeatureMap[Def] = i;
+ FeatureMap[Def] = I;
}
OS << " "
@@ -201,9 +201,9 @@ static void printFeatureMask(raw_ostream &OS,
}
OS << "{ { { ";
- for (unsigned i = 0; i != Mask.size(); ++i) {
+ for (unsigned I = 0; I != Mask.size(); ++I) {
OS << "0x";
- OS.write_hex(Mask[i]);
+ OS.write_hex(Mask[I]);
OS << "ULL, ";
}
OS << "} } }";
@@ -211,7 +211,7 @@ static void printFeatureMask(raw_ostream &OS,
/// Emit some information about the SubtargetFeature as calls to a macro so
/// that they can be used from C++.
-void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) {
+void SubtargetEmitter::emitSubtargetInfoMacroCalls(raw_ostream &OS) {
OS << "\n#ifdef GET_SUBTARGETINFO_MACRO\n";
std::vector<const Record *> FeatureList =
@@ -252,7 +252,7 @@ void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) {
// FeatureKeyValues - Emit data of all the subtarget features. Used by the
// command line.
//
-unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS,
+unsigned SubtargetEmitter::featureKeyValues(raw_ostream &OS,
const FeatureMapTy &FeatureMap) {
std::vector<const Record *> FeatureList =
Records.getAllDerivedDefinitions("SubtargetFeature");
@@ -301,7 +301,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS,
// CPUKeyValues - Emit data of all the subtarget processors. Used by command
// line.
//
-unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
+unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS,
const FeatureMapTy &FeatureMap) {
// Gather and sort processor information
std::vector<const Record *> ProcessorList =
@@ -349,7 +349,7 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
// data initialization for the specified itinerary. N is the number
// of stages.
//
-void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
+void SubtargetEmitter::formItineraryStageString(const std::string &Name,
const Record *ItinData,
std::string &ItinString,
unsigned &NStages) {
@@ -358,9 +358,9 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
// For each stage
unsigned N = NStages = StageList.size();
- for (unsigned i = 0; i < N;) {
+ for (unsigned I = 0; I < N;) {
// Next stage
- const Record *Stage = StageList[i];
+ const Record *Stage = StageList[I];
// Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
int Cycles = Stage->getValueAsInt("Cycles");
@@ -370,10 +370,10 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
ConstRecVec UnitList = Stage->getValueAsListOfDefs("Units");
// For each unit
- for (unsigned j = 0, M = UnitList.size(); j < M;) {
+ for (unsigned J = 0, M = UnitList.size(); J < M;) {
// Add name and bitwise or
- ItinString += Name + "FU::" + UnitList[j]->getName().str();
- if (++j < M)
+ ItinString += Name + "FU::" + UnitList[J]->getName().str();
+ if (++J < M)
ItinString += " | ";
}
@@ -385,7 +385,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
// Close off stage
ItinString += " }";
- if (++i < N)
+ if (++I < N)
ItinString += ", ";
}
}
@@ -395,7 +395,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
// operand cycle initialization for the specified itinerary. N is the
// number of operands that has cycles specified.
//
-void SubtargetEmitter::FormItineraryOperandCycleString(
+void SubtargetEmitter::formItineraryOperandCycleString(
const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) {
// Get operand cycle list
std::vector<int64_t> OperandCycleList =
@@ -411,19 +411,19 @@ void SubtargetEmitter::FormItineraryOperandCycleString(
}
}
-void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
+void SubtargetEmitter::formItineraryBypassString(const std::string &Name,
const Record *ItinData,
std::string &ItinString,
unsigned NOperandCycles) {
ConstRecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses");
unsigned N = BypassList.size();
- unsigned i = 0;
+ unsigned I = 0;
ListSeparator LS;
- for (; i < N; ++i) {
+ for (; I < N; ++I) {
ItinString += LS;
- ItinString += Name + "Bypass::" + BypassList[i]->getName().str();
+ ItinString += Name + "Bypass::" + BypassList[I]->getName().str();
}
- for (; i < NOperandCycles; ++i) {
+ for (; I < NOperandCycles; ++I) {
ItinString += LS;
ItinString += " 0";
}
@@ -434,7 +434,7 @@ void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
// by CodeGenSchedClass::Index.
//
-void SubtargetEmitter::EmitStageAndOperandCycleData(
+void SubtargetEmitter::emitStageAndOperandCycleData(
raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
// Multiple processor models may share an itinerary record. Emit it once.
SmallPtrSet<const Record *, 8> ItinsDefSet;
@@ -453,9 +453,9 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
OS << "\n// Functional units for \"" << Name << "\"\n"
<< "namespace " << Name << "FU {\n";
- for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
- OS << " const InstrStage::FuncUnits " << FUs[j]->getName()
- << " = 1ULL << " << j << ";\n";
+ for (unsigned J = 0, FUN = FUs.size(); J < FUN; ++J)
+ OS << " const InstrStage::FuncUnits " << FUs[J]->getName()
+ << " = 1ULL << " << J << ";\n";
OS << "} // end namespace " << Name << "FU\n";
@@ -466,8 +466,8 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
<< "namespace " << Name << "Bypass {\n";
OS << " const unsigned NoBypass = 0;\n";
- for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
- OS << " const unsigned " << BPs[j]->getName() << " = 1 << " << j
+ for (unsigned J = 0, BPN = BPs.size(); J < BPN; ++J)
+ OS << " const unsigned " << BPs[J]->getName() << " = 1 << " << J
<< ";\n";
OS << "} // end namespace " << Name << "Bypass\n";
@@ -518,7 +518,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
std::string ItinStageString;
unsigned NStages = 0;
if (ItinData)
- FormItineraryStageString(std::string(Name), ItinData, ItinStageString,
+ formItineraryStageString(std::string(Name), ItinData, ItinStageString,
NStages);
// Get string and operand cycle count
@@ -526,10 +526,10 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
unsigned NOperandCycles = 0;
std::string ItinBypassString;
if (ItinData) {
- FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
+ formItineraryOperandCycleString(ItinData, ItinOperandCycleString,
NOperandCycles);
- FormItineraryBypassString(std::string(Name), ItinData, ItinBypassString,
+ formItineraryBypassString(std::string(Name), ItinData, ItinBypassString,
NOperandCycles);
}
@@ -610,7 +610,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
// Itineraries for each processor. The Itinerary lists are indexed on
// CodeGenSchedClass::Index.
//
-void SubtargetEmitter::EmitItineraries(
+void SubtargetEmitter::emitItineraries(
raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {
// Multiple processor models may share an itinerary record. Emit it once.
SmallPtrSet<const Record *, 8> ItinsDefSet;
@@ -642,15 +642,15 @@ void SubtargetEmitter::EmitItineraries(
OS << ItinsDef->getName() << "[] = {\n";
// For each itinerary class in CodeGenSchedClass::Index order.
- for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
- InstrItinerary &Intinerary = ItinList[j];
+ for (unsigned J = 0, M = ItinList.size(); J < M; ++J) {
+ InstrItinerary &Intinerary = ItinList[J];
// Emit Itinerary in the form of
// { firstStage, lastStage, firstCycle, lastCycle } // index
OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage
<< ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle
<< ", " << Intinerary.LastOperandCycle << " }"
- << ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
+ << ", // " << J << " " << SchedModels.getSchedClass(J).Name << "\n";
}
// End processor itinerary table
OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
@@ -662,7 +662,7 @@ void SubtargetEmitter::EmitItineraries(
// Emit either the value defined in the TableGen Record, or the default
// value defined in the C++ header. The Record is null if the processor does not
// define a model.
-void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
+void SubtargetEmitter::emitProcessorProp(raw_ostream &OS, const Record *R,
StringRef Name, char Separator) {
OS << " ";
int V = R ? R->getValueAsInt(Name) : -1;
@@ -673,14 +673,14 @@ void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
OS << '\n';
}
-void SubtargetEmitter::EmitProcessorResourceSubUnits(
+void SubtargetEmitter::emitProcessorResourceSubUnits(
const CodeGenProcModel &ProcModel, raw_ostream &OS) {
OS << "\nstatic const unsigned " << ProcModel.ModelName
<< "ProcResourceSubUnits[] = {\n"
<< " 0, // Invalid\n";
- for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
- const Record *PRDef = ProcModel.ProcResourceDefs[i];
+ for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
+ const Record *PRDef = ProcModel.ProcResourceDefs[I];
if (!PRDef->isSubClassOf("ProcResGroup"))
continue;
for (const Record *RUDef : PRDef->getValueAsListOfDefs("Resources")) {
@@ -695,7 +695,7 @@ void SubtargetEmitter::EmitProcessorResourceSubUnits(
OS << "};\n";
}
-static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
+static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
raw_ostream &OS) {
int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0;
if (const Record *RCU = ProcModel.RetireControlUnit) {
@@ -709,7 +709,7 @@ static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n ";
}
-static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel,
+static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel,
unsigned NumRegisterFiles,
unsigned NumCostEntries, raw_ostream &OS) {
if (NumRegisterFiles)
@@ -726,7 +726,7 @@ static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel,
}
unsigned
-SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
+SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel,
raw_ostream &OS) {
if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
return RF.hasDefaultCosts();
@@ -778,7 +778,7 @@ SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
return CostTblIndex;
}
-void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
+void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
raw_ostream &OS) {
unsigned QueueID = 0;
if (ProcModel.LoadQueue) {
@@ -798,33 +798,33 @@ void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n";
}
-void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
+void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
raw_ostream &OS) {
// Generate a table of register file descriptors (one entry per each user
// defined register file), and a table of register costs.
- unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS);
+ unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS);
// Now generate a table for the extra processor info.
OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
<< "ExtraInfo = {\n ";
// Add information related to the retire control unit.
- EmitRetireControlUnitInfo(ProcModel, OS);
+ emitRetireControlUnitInfo(ProcModel, OS);
// Add information related to the register files (i.e. where to find register
// file descriptors and register costs).
- EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
+ emitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
NumCostEntries, OS);
// Add information about load/store queues.
- EmitLoadStoreQueueInfo(ProcModel, OS);
+ emitLoadStoreQueueInfo(ProcModel, OS);
OS << "};\n";
}
-void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
+void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel,
raw_ostream &OS) {
- EmitProcessorResourceSubUnits(ProcModel, OS);
+ emitProcessorResourceSubUnits(ProcModel, OS);
OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
@@ -833,8 +833,8 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
<< " {\"InvalidUnit\", 0, 0, 0, 0},\n";
unsigned SubUnitsOffset = 1;
- for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
- const Record *PRDef = ProcModel.ProcResourceDefs[i];
+ for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
+ const Record *PRDef = ProcModel.ProcResourceDefs[I];
const Record *SuperDef = nullptr;
unsigned SuperIdx = 0;
@@ -866,7 +866,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
} else {
OS << "nullptr";
}
- OS << "}, // #" << i + 1;
+ OS << "}, // #" << I + 1;
if (SuperDef)
OS << ", Super=" << SuperDef->getName();
OS << "\n";
@@ -877,7 +877,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
// Find the WriteRes Record that defines processor resources for this
// SchedWrite.
const Record *
-SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
+SubtargetEmitter::findWriteResources(const CodeGenSchedRW &SchedWrite,
const CodeGenProcModel &ProcModel) {
// Check if the SchedWrite is already subtarget-specific and directly
@@ -938,7 +938,7 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
/// Find the ReadAdvance record for the given SchedRead on this processor or
/// return NULL.
const Record *
-SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
+SubtargetEmitter::findReadAdvance(const CodeGenSchedRW &SchedRead,
const CodeGenProcModel &ProcModel) {
// Check for SchedReads that directly specify a ReadAdvance.
if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
@@ -997,12 +997,12 @@ SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
// Expand an explicit list of processor resources into a full list of implied
// resource groups and super resources that cover them.
-void SubtargetEmitter::ExpandProcResources(
+void SubtargetEmitter::expandProcResources(
ConstRecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {
assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");
- for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
- const Record *PRDef = PRVec[i];
+ for (unsigned I = 0, E = PRVec.size(); I != E; ++I) {
+ const Record *PRDef = PRVec[I];
ConstRecVec SubResources;
if (PRDef->isSubClassOf("ProcResGroup"))
SubResources = PRDef->getValueAsListOfDefs("Resources");
@@ -1019,8 +1019,8 @@ void SubtargetEmitter::ExpandProcResources(
const Record *SuperDef = SchedModels.findProcResUnits(
SubDef->getValueAsDef("Super"), PM, SubDef->getLoc());
PRVec.push_back(SuperDef);
- ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
- AcquireAtCycles.push_back(AcquireAtCycles[i]);
+ ReleaseAtCycles.push_back(ReleaseAtCycles[I]);
+ AcquireAtCycles.push_back(AcquireAtCycles[I]);
SubDef = SuperDef;
}
}
@@ -1036,8 +1036,8 @@ void SubtargetEmitter::ExpandProcResources(
}
if (SubI == SubE) {
PRVec.push_back(PR);
- ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
- AcquireAtCycles.push_back(AcquireAtCycles[i]);
+ ReleaseAtCycles.push_back(ReleaseAtCycles[I]);
+ AcquireAtCycles.push_back(AcquireAtCycles[I]);
}
}
}
@@ -1045,7 +1045,7 @@ void SubtargetEmitter::ExpandProcResources(
// Generate the SchedClass table for this processor and update global
// tables. Must be called for each processor in order.
-void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
+void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,
SchedClassTables &SchedTables) {
std::vector<MCSchedClassDesc> &SCTab =
SchedTables.ProcSchedClasses.emplace_back();
@@ -1147,7 +1147,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
for (unsigned WS : WriteSeq) {
const Record *WriteRes =
- FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
+ findWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
// Mark the parent class as invalid for unsupported write types.
if (WriteRes->getValueAsBit("Unsupported")) {
@@ -1209,7 +1209,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
- ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
+ expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
for (unsigned PRIdx = 0, PREnd = PRVec.size(); PRIdx != PREnd;
@@ -1263,7 +1263,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx;
++UseIdx) {
const Record *ReadAdvance =
- FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
+ findReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
if (!ReadAdvance)
continue;
@@ -1323,12 +1323,12 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
SchedTables.WriteLatencies.begin(), SchedTables.WriteLatencies.end(),
WriteLatencies.begin(), WriteLatencies.end());
if (WLPos != SchedTables.WriteLatencies.end()) {
- unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
- SCDesc.WriteLatencyIdx = idx;
- for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
- if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
+ unsigned Idx = WLPos - SchedTables.WriteLatencies.begin();
+ SCDesc.WriteLatencyIdx = Idx;
+ for (unsigned I = 0, E = WriteLatencies.size(); I < E; ++I)
+ if (SchedTables.WriterNames[Idx + I].find(WriterNames[I]) ==
std::string::npos) {
- SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
+ SchedTables.WriterNames[Idx + I] += std::string("_") + WriterNames[I];
}
} else {
SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
@@ -1351,7 +1351,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
}
// Emit SchedClass tables for all processors and associated global tables.
-void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
+void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,
raw_ostream &OS) {
// Emit global WriteProcResTable.
OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
@@ -1446,15 +1446,15 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
}
}
-void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
+void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {
// For each processor model.
for (const CodeGenProcModel &PM : SchedModels.procModels()) {
// Emit extra processor info if available.
if (PM.hasExtraProcessorInfo())
- EmitExtraProcessorInfo(PM, OS);
+ emitExtraProcessorInfo(PM, OS);
// Emit processor resource table.
if (PM.hasInstrSchedModel())
- EmitProcessorResources(PM, OS);
+ emitProcessorResources(PM, OS);
else if (!PM.ProcResourceDefs.empty())
PrintFatalError(PM.ModelDef->getLoc(),
"SchedMachineModel defines "
@@ -1463,12 +1463,12 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
// Begin processor itinerary properties
OS << "\n";
OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
- EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');
- EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');
- EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');
- EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');
- EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');
- EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');
+ emitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');
+ emitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');
+ emitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');
+ emitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');
+ emitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');
+ emitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');
bool PostRAScheduler =
(PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false);
@@ -1516,7 +1516,7 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
//
// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
//
-void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
+void SubtargetEmitter::emitSchedModel(raw_ostream &OS) {
OS << "#ifdef DBGFIELD\n"
<< "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
<< "#endif\n"
@@ -1529,22 +1529,22 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
if (SchedModels.hasItineraries()) {
std::vector<std::vector<InstrItinerary>> ProcItinLists;
// Emit the stage data
- EmitStageAndOperandCycleData(OS, ProcItinLists);
- EmitItineraries(OS, ProcItinLists);
+ emitStageAndOperandCycleData(OS, ProcItinLists);
+ emitItineraries(OS, ProcItinLists);
}
OS << "\n// ===============================================================\n"
<< "// Data tables for the new per-operand machine model.\n";
SchedClassTables SchedTables;
for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
- GenSchedClassTables(ProcModel, SchedTables);
+ genSchedClassTables(ProcModel, SchedTables);
}
- EmitSchedClassTables(SchedTables, OS);
+ emitSchedClassTables(SchedTables, OS);
OS << "\n#undef DBGFIELD\n";
// Emit the processor machine model
- EmitProcessorModels(OS);
+ emitProcessorModels(OS);
}
static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
@@ -1756,7 +1756,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl(
emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);
}
-void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
+void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,
raw_ostream &OS) {
OS << "unsigned " << ClassName
<< "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
@@ -1786,7 +1786,7 @@ void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName,
PE.expandSTIPredicate(OS, Fn);
}
-void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
+void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName,
raw_ostream &OS) {
const CodeGenHwModes &CGH = TGT.getHwModes();
assert(CGH.getNumModeIds() > 0);
@@ -1825,7 +1825,7 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
OS << " return Modes;\n}\n";
// End emitting for getHwModeSet().
- auto handlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) {
+ auto HandlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) {
OS << " case HwMode_" << ModeType << ":\n"
<< " Modes &= " << ModeInBitSet << ";\n"
<< " if (!Modes)\n return Modes;\n"
@@ -1842,9 +1842,9 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
OS << " if (!Modes)\n return Modes;\n\n";
OS << " switch (type) {\n";
OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n";
- handlePerMode("ValueType", ValueTypeModes);
- handlePerMode("RegInfo", RegInfoModes);
- handlePerMode("EncodingInfo", EncodingInfoModes);
+ HandlePerMode("ValueType", ValueTypeModes);
+ HandlePerMode("RegInfo", RegInfoModes);
+ HandlePerMode("EncodingInfo", EncodingInfoModes);
OS << " }\n";
OS << " llvm_unreachable(\"unexpected HwModeType\");\n"
<< " return 0; // should not get here\n}\n";
@@ -1871,7 +1871,7 @@ void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName,
// Produces a subtarget specific function for parsing
// the subtarget features string.
-void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
+void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {
ArrayRef<const Record *> Features =
Records.getAllDerivedDefinitions("SubtargetFeature");
@@ -1951,10 +1951,10 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
<< " return MCSubtargetInfo::isCPUStringValid(CPU);\n"
<< " }\n";
OS << "};\n";
- EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
+ emitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
}
-void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) {
+void SubtargetEmitter::emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS) {
OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n";
OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n";
@@ -1988,18 +1988,18 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "#undef GET_SUBTARGETINFO_ENUM\n\n";
OS << "namespace llvm {\n";
- auto FeatureMap = Enumeration(OS);
+ auto FeatureMap = enumeration(OS);
OS << "} // end namespace llvm\n\n";
OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
- EmitSubtargetInfoMacroCalls(OS);
+ emitSubtargetInfoMacroCalls(OS);
OS << "namespace llvm {\n";
- unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap);
+ unsigned NumFeatures = featureKeyValues(OS, FeatureMap);
OS << "\n";
- EmitSchedModel(OS);
+ emitSchedModel(OS);
OS << "\n";
- unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
+ unsigned NumProcs = cpuKeyValues(OS, FeatureMap);
OS << "\n";
// MCInstrInfo initialization routine.
@@ -2045,7 +2045,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
if (Target == "AArch64")
OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
- ParseFeaturesFunction(OS);
+ parseFeaturesFunction(OS);
OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
@@ -2140,15 +2140,15 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "nullptr, nullptr, nullptr";
OS << ") {}\n\n";
- EmitSchedModelHelpers(ClassName, OS);
- EmitHwModeCheck(ClassName, OS);
+ emitSchedModelHelpers(ClassName, OS);
+ emitHwModeCheck(ClassName, OS);
emitGetMacroFusions(ClassName, OS);
OS << "} // end namespace llvm\n\n";
OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
- EmitMCInstrAnalysisPredicateFunctions(OS);
+ emitMcInstrAnalysisPredicateFunctions(OS);
}
static TableGen::Emitter::OptClass<SubtargetEmitter>
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index fff4c6b7c27ada..bea2a2e735dbe2 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -39,17 +39,17 @@ static cl::opt<std::string> Class("class",
cl::value_desc("class name"),
cl::cat(PrintEnumsCat));
-static void PrintRecords(const RecordKeeper &Records, raw_ostream &OS) {
+static void printRecords(const RecordKeeper &Records, raw_ostream &OS) {
OS << Records; // No argument, dump all contents
}
-static void PrintEnums(const RecordKeeper &Records, raw_ostream &OS) {
+static void printEnums(const RecordKeeper &Records, raw_ostream &OS) {
for (const Record *Rec : Records.getAllDerivedDefinitions(Class))
OS << Rec->getName() << ", ";
OS << "\n";
}
-static void PrintSets(const RecordKeeper &Records, raw_ostream &OS) {
+static void printSets(const RecordKeeper &Records, raw_ostream &OS) {
SetTheory Sets;
Sets.addFieldExpander("Set", "Elements");
for (const Record *Rec : Records.getAllDerivedDefinitions("Set")) {
@@ -63,15 +63,15 @@ static void PrintSets(const RecordKeeper &Records, raw_ostream &OS) {
}
static TableGen::Emitter::Opt X[] = {
- {"print-records", PrintRecords, "Print all records to stdout (default)",
+ {"print-records", printRecords, "Print all records to stdout (default)",
true},
{"print-detailed-records", EmitDetailedRecords,
"Print full details of all records to stdout"},
{"null-backend", [](const RecordKeeper &Records, raw_ostream &OS) {},
"Do nothing after parsing (useful for timing)"},
{"dump-json", EmitJSON, "Dump all records as machine-readable JSON"},
- {"print-enums", PrintEnums, "Print enum values for a class"},
- {"print-sets", PrintSets, "Print expanded sets for testing DAG exprs"},
+ {"print-enums", printEnums, "Print enum values for a class"},
+ {"print-sets", printSets, "Print expanded sets for testing DAG exprs"},
};
int main(int argc, char **argv) {
diff --git a/llvm/utils/TableGen/VTEmitter.cpp b/llvm/utils/TableGen/VTEmitter.cpp
index 8f4bcd5fccc73d..5f24f0c86c6486 100644
--- a/llvm/utils/TableGen/VTEmitter.cpp
+++ b/llvm/utils/TableGen/VTEmitter.cpp
@@ -29,7 +29,7 @@ class VTEmitter {
} // End anonymous namespace.
-static void VTtoGetLLVMTyString(raw_ostream &OS, const Record *VT) {
+static void vTtoGetLlvmTyString(raw_ostream &OS, const Record *VT) {
bool IsVector = VT->getValueAsBit("isVector");
bool IsRISCVVecTuple = VT->getValueAsBit("isRISCVVecTuple");
@@ -208,7 +208,7 @@ void VTEmitter::run(raw_ostream &OS) {
continue;
OS << " GET_VT_EVT(" << VT->getValueAsString("LLVMName") << ", ";
- VTtoGetLLVMTyString(OS, VT);
+ vTtoGetLlvmTyString(OS, VT);
OS << ")\n";
}
OS << "#endif\n\n";
>From 2d7062991b1b9e0957169cfdce3738dee074247d Mon Sep 17 00:00:00 2001
From: Jerry Sun <sunyiran0817 at gmail.com>
Date: Mon, 28 Oct 2024 17:04:19 -0400
Subject: [PATCH 2/2] change Arm to ARM in function declarition
---
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index fe8a82e6d7e617..792d047139466c 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -53,7 +53,7 @@ static void checkFeatureTree(const Record *Root) {
}
}
-static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
// Look through all SubtargetFeature defs with the given FieldName, and
@@ -343,5 +343,5 @@ static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
}
static TableGen::Emitter::Opt
- X("gen-arm-target-def", emitArmTargetDef,
+ X("gen-arm-target-def", emitARMTargetDef,
"Generate the ARM or AArch64 Architecture information header.");
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