[llvm] [TableGen] Make `!and` short-circuit when either of the operand is zero (PR #113963)

[Rahul Joshi via llvm-commits]

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@@ -1543,6 +1543,23 @@ const Init *BinOpInit::resolveReferences(Resolver &R) const {
   const Init *lhs = LHS->resolveReferences(R);
   const Init *rhs = RHS->resolveReferences(R);
 
+  if (getOpcode() == AND) {
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jurahul wrote:

Do we need similar short circuit for OR as well? 

https://github.com/llvm/llvm-project/pull/113963