[llvm] [RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (PR #113756)

[Camel Coder via llvm-commits]

camel-cdr wrote:

@topperc 

> > Although one thing to consider is that ooo implementations will need to predict vtype/vl, and this may fill up the predictors quicker.
> 
> Do you know of ooo implementations implementing a predictor?

Yes, Steam Computing open-sourced an ooo implementation with CSR speculation on top of BOOM: https://github.com/riscv-stc/riscv-boom/tree/matrix

![image](https://github.com/user-attachments/assets/2067fd13-7e3c-470b-9da3-7fcce7f45f96)


Their default configuration seems to have 8 entries for vconfig speculation:
https://github.com/riscv-stc/riscv-boom/blob/8ccc5906f27d680ee9ef1b89f9a221da7b10f5df/src/main/scala/common/config-mixins.scala#L567C15-L567C30

I was not able to build it with verilator and contacted the author, who said that they only support vcs, which I don't have access to.
If someone here has a license, I can share my Dockerfile that got the farthest along the build process with verilator.

I would hope there are a lot of proprietary cores with vtype speculation currently in development as well.


https://github.com/llvm/llvm-project/pull/113756