[llvm] [PowerPC][LLC] change the default cpu to power7 for AIX OS (PR #113943)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 28 11:20:33 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-binary-utilities
Author: zhijian lin (diggerlin)
<details>
<summary>Changes</summary>
The `PPCTargetParser` was added in https://github.com/llvm/llvm-project/pull/97541.
we use the same default CPU and CPU features with same interfaces for llc. And The patch will also change the default cpu to power7 for llc in AIX OS.
---
Patch is 60.79 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113943.diff
70 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCSubtarget.cpp (+3-5)
- (modified) llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/Frames-large.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-dwarf.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/alloca-oversized.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/atomic-float.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/atomics-indexed.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/atomics.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/fma-assoc.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/frounds.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ftrunc-legalize.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/hoist-logic.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/huge-frame-call.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/inc-of-add.ll (+3-3)
- (modified) llvm/test/CodeGen/PowerPC/kill_flag_verification.ll (+3-3)
- (modified) llvm/test/CodeGen/PowerPC/ldst-16-byte.mir (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/legalize-vaarg.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/licm-tocReg.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/noredzone.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/peephole-mma-phi-liveness.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/popcnt-zext.ll (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ppc64-nest.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ppc64-varargs.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ppcsoftops.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/pr43976.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/pr47660.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/pr74951.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/store-forward-be32.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/store-forward-be64.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/sub-of-not.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/toc-data-common.ll (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/toc-data-const.ll (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/toc-data.ll (+12-12)
- (modified) llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/vec-trunc2.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll (+1-1)
- (modified) llvm/test/DebugInfo/XCOFF/empty.ll (+3-4)
- (modified) llvm/test/DebugInfo/XCOFF/explicit-section.ll (+1-1)
- (modified) llvm/test/DebugInfo/XCOFF/function-sections.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll (+1-1)
- (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll (+1-1)
- (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected (+2-2)
- (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected (+2-2)
- (modified) llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbolize-operands.ll (+1-1)
- (modified) llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbolize-operands2.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index f2fee2ce7c6a8a..e6edac8b142f48 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -29,6 +29,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/TargetParser/PPCTargetParser.h"
#include <cstdlib>
using namespace llvm;
@@ -79,13 +80,10 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
// Determine default and user specified characteristics
std::string CPUName = std::string(CPU);
if (CPUName.empty() || CPU == "generic") {
- // If cross-compiling with -march=ppc64le without -mcpu
- if (TargetTriple.getArch() == Triple::ppc64le)
- CPUName = "ppc64le";
- else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
+ if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
CPUName = "e500";
else
- CPUName = "generic";
+ CPUName = std::string(PPC::getNormalizedPPCTargetCPU(TargetTriple));
}
// Determine the CPU to schedule for.
diff --git a/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll b/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
index 2f25f12a13b5b5..df32a406d2ba33 100644
--- a/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
+++ b/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
@@ -6,7 +6,7 @@ target triple = "powerpc-ibm-aix7.2.0.0"
; Check IndexedReference::computeRefCost can handle type differences between
; CacheLineSize and Numerator
-; CHECK: Loop '_loop_1_do_' has cost = 2
+; CHECK: Loop '_loop_1_do_' has cost = 1
%_elem_type_of_v = type <{ i32 }>
diff --git a/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
index db4e22fd8d17af..6f2b0aa0d6308e 100644
--- a/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
+++ b/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
+; RUN: llc -mcpu=ppc -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
;; Formerly crashed, see PR 1508
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll b/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
index 61097f0ef7c068..ae28124b3c9c30 100644
--- a/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
+++ b/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PPC32-LINUX
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=PPC64-LINUX
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc | FileCheck %s -check-prefix=PPC64-LINUX
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -frame-pointer=all | FileCheck %s -check-prefix=PPC32-LINUX
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -frame-pointer=all | FileCheck %s -check-prefix=PPC64-LINUX
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc -frame-pointer=all | FileCheck %s -check-prefix=PPC64-LINUX
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PPC32-LINUX
; RUN: llc < %s -mcpu=pwr4 -mattr=-altivec -verify-machineinstrs \
diff --git a/llvm/test/CodeGen/PowerPC/Frames-large.ll b/llvm/test/CodeGen/PowerPC/Frames-large.ll
index 7d15c02be43186..e1bf8bd072c8d0 100644
--- a/llvm/test/CodeGen/PowerPC/Frames-large.ll
+++ b/llvm/test/CodeGen/PowerPC/Frames-large.ll
@@ -4,10 +4,10 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: -frame-pointer=all | FileCheck %s -check-prefix=PPC32-LINUX-FP
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | \
+; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu | \
; RUN: FileCheck %s -check-prefix=PPC64-LINUX-NOFP
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -frame-pointer=all | FileCheck %s -check-prefix=PPC64-LINUX-FP
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
diff --git a/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll b/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
index 7a3ef75f0aae14..76b40aad669028 100644
--- a/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
+++ b/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
@@ -2,7 +2,7 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-LE
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: llc -verify-machineinstrs -mcpu=ppc -mcpu=ppc -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE
; RUN: opt --passes='sroa,loop-vectorize,loop-unroll,instcombine' -S \
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index ccc36530c7957b..4f4eea60973d03 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=32BIT %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=64BIT %s
define void @call_test_chars() {
diff --git a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
index 33e61a8cab3765..59a9e87c6c0587 100644
--- a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=generic -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefixes=SEC,SEC32
; RUN: llvm-objdump -r %t.o | FileCheck %s --check-prefix=RELO
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=generic -filetype=obj -o %t64.o < %s
; RUN: llvm-readobj --section-headers %t64.o | FileCheck %s --check-prefixes=SEC,SEC64
; RUN: llvm-objdump -r %t64.o | FileCheck %s --check-prefix=RELO64
diff --git a/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll b/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll
index 8e3b99b6114daa..d6aad918651efb 100644
--- a/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -verify-machineinstrs < %s | FileCheck %s
@llvm.global_ctors = appending global [5 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @cf1, ptr null }, { i32, ptr, ptr } { i32 21, ptr @cf2, ptr null }, { i32, ptr, ptr } { i32 81, ptr @cf3, ptr null }, { i32, ptr, ptr } { i32 1125, ptr @cf4, ptr null }, { i32, ptr, ptr } { i32 64512, ptr @cf5, ptr null }]
@llvm.global_dtors = appending global [5 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 20, ptr @df1, ptr null }, { i32, ptr, ptr } { i32 80, ptr @df2, ptr null }, { i32, ptr, ptr } { i32 1124, ptr @df3, ptr null }, { i32, ptr, ptr } { i32 64511, ptr @df4, ptr null }, { i32, ptr, ptr } { i32 65535, ptr @df5, ptr null }]
diff --git a/llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll
index 6b941917d6c310..942ab92a3b4215 100644
--- a/llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -dr %t.o | FileCheck --check-prefix=OBJ32 %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
; RUN: llvm-objdump -dr %t.o | FileCheck --check-prefix=OBJ64 %s
; Function Attrs: noinline nounwind optnone
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll
index 9c5d560e27f91e..7b66148044ddcc 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll
@@ -1,9 +1,9 @@
; This file contains exception section testing for when debug information is present.
; The 32-bit test should not print exception auxilliary entries because they are a 64-bit only feature.
; Exception auxilliary entries are present in the 64-bit tests because 64-bit && debug enabled are the requirements.
-; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t_32.o < %s
+; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t_32.o < %s
; RUN: llvm-readobj --syms %t_32.o | FileCheck %s --check-prefix=SYMS32
-; RUN: llc -mtriple=powerpc64-unknown-aix -filetype=obj -o %t_32.o < %s
+; RUN: llc -mtriple=powerpc64-unknown-aix -mcpu=ppc -filetype=obj -o %t_32.o < %s
; RUN: llvm-readobj --syms %t_32.o | FileCheck %s --check-prefix=SYMS64
; If any debug information is included in a module and is XCOFF64, exception auxilliary entries are emitted
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll
index 8ee58755919b7f..fbcb62a49f9720 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll
@@ -1,11 +1,11 @@
; Testing 32-bit and 64-bit exception section entries, no exception auxilliary
; entries should be produced as no debug information is specified.
-; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t_32.o < %s
+; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t_32.o < %s
; RUN: llvm-readobj --exception-section %t_32.o | FileCheck %s --check-prefix=EXCEPT
; RUN: llvm-readobj --section-headers %t_32.o | FileCheck %s --check-prefix=READ
; RUN: llvm-readobj --syms %t_32.o | FileCheck %s --check-prefix=SYMS
-; RUN: llc -mtriple=powerpc64-unknown-aix -filetype=obj -o %t_64.o < %s
+; RUN: llc -mtriple=powerpc64-unknown-aix -mcpu=ppc -filetype=obj -o %t_64.o < %s
; RUN: llvm-readobj --exception-section %t_64.o | FileCheck %s --check-prefix=EXCEPT64
; RUN: llvm-readobj --section-headers %t_64.o | FileCheck %s --check-prefix=READ64
; RUN: llvm-readobj --syms %t_64.o | FileCheck %s --check-prefix=SYMS64
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
index 7ffd11f485e429..030356e4d30426 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
@@ -3,10 +3,10 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec -data-sections=false < %s |\
; RUN: FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj %s -o %t.o
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj %s -o %t.o
; RUN: llvm-readobj --syms --auxiliary-header %t.o | FileCheck %s --check-prefixes=SYM,AUX32
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj %s -o %t64.o
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -filetype=obj %s -o %t64.o
; RUN: llvm-readobj --syms --auxiliary-header %t64.o | FileCheck %s --check-prefixes=SYM,AUX64
@b = global i32 0, align 4
diff --git a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
index bf66a1ed042d22..3c1b28a4eff1cb 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=ASM32 %s
-; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
+; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr {
; ASM32-LABEL: int_va_arg:
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
index 5ffa852d3d57fc..1b9c66ad0b234d 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=64BIT %s
; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
diff --git a/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir b/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
index 7d96f7feabe2be..c295add57c9c0a 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
+++ b/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
@@ -1,6 +1,6 @@
# REQUIRES: asserts
# RUN: llc -verify-machineinstrs -simplify-mir -mtriple=powerpc64-ibm-aix-xcoff \
-# RUN: -debug-only=regalloc %s -o - 2>&1 | FileCheck %s
+# RUN: -mcpu=ppc -debug-only=regalloc %s -o - 2>&1 | FileCheck %s
---
name: i64
@@ -19,4 +19,4 @@ body: |
# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x1
# CHECK-DAG: 4 ]
-# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
\ No newline at end of file
+# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
diff --git a/llvm/test/CodeGen/PowerPC/alloca-oversized.ll b/llvm/test/CodeGen/PowerPC/alloca-oversized.ll
index 89922c34838586..d10c66bced3e23 100644
--- a/llvm/test/CodeGen/PowerPC/alloca-oversized.ll
+++ b/llvm/test/CodeGen/PowerPC/alloca-oversized.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
+; RUN: llc < %s -mcpu=generic -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
define void @test_oversized(ptr %dst, i32 %cond) {
; CHECK-LABEL: test_oversized:
; CHECK: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/PowerPC/atomic-float.ll b/llvm/test/CodeGen/PowerPC/atomic-float.ll
index 8f9c86fb8a8b85..0158ba8652dd14 100644
--- a/llvm/test/CodeGen/PowerPC/atomic-float.ll
+++ b/llvm/test/CodeGen/PowerPC/atomic-float.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: llc -verify-machineinstrs -mcpu=generic -mtriple=powerpc64-unknown-unknown \
; RUN: < %s | FileCheck --check-prefix=CHECK-64 %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown \
+; RUN: llc -verify-machineinstrs -mcpu=generic -mtriple=powerpc-unknown-unknown \
; RUN: < %s | FileCheck --check-prefix=CHECK-32 %s
define float @test_add(ptr %ptr, float %incr) {
diff --git a/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
index 933311140465f5..0ff2f28207ed47 100644
--- a/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
+++ b/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
; CHECK-LABEL: atomicrmw_usub_cond_i8:
diff --git a/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
index 505ac8639595fd..2882dc420b6084 100644
--- a/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-LABEL: atomicrmw_uinc_wrap_i8:
diff --git a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
index 986c0de2fb4923..f6d63255d769b8 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
; This is already checked for in Atomics-64.ll
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
+; RUN: llc < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
; In this file, we check that atomic load/store can make use of the indexed
; versions of the instructions.
diff --git a/llvm/test/CodeGen/PowerPC/atomics.ll b/llvm/test/CodeGen/PowerPC/atomics.ll
index ff5bec53acd257..07bdbb25a746a5 100644
--- a/llvm/test/CodeGen/PowerPC/atomics.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
; This is already checked for in Atomics-64.ll
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
+; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
; FIXME: we don't currently check for the operations themselves with CHECK-NEXT,
; because they are implemented in a very messy way with lwarx/stwcx.
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
index 443f65ce1cd6c1..1a64b...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/113943
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