[llvm] [LLVM][AArch64] Add assembly/disassembly for MUL/BFMUL SME instructions (PR #113535)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 28 09:56:00 PDT 2024
https://github.com/CarolineConcatto updated https://github.com/llvm/llvm-project/pull/113535
>From 4bc9256c0d972a834788a94be51d809b96b87d9e Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.concatto at arm.com>
Date: Thu, 24 Oct 2024 09:14:26 +0000
Subject: [PATCH 1/2] [LLVM][AArch64] Add assembly/disassembly for MUL/BFMUL
SME instructions
According to https://developer.arm.com/documentation/ddi0602
Co-authored-by: Momchil-Velikov Momchil.Velikov at arm.com
---
.../lib/Target/AArch64/AArch64SMEInstrInfo.td | 10 +
llvm/lib/Target/AArch64/SMEInstrFormats.td | 110 ++++++++
llvm/test/MC/AArch64/SME2/bfmul-diagnostics.s | 111 ++++++++
llvm/test/MC/AArch64/SME2/bfmul.s | 92 ++++++
llvm/test/MC/AArch64/SME2/fmul-diagnostics.s | 112 ++++++++
llvm/test/MC/AArch64/SME2/fmul.s | 261 ++++++++++++++++++
6 files changed, 696 insertions(+)
create mode 100644 llvm/test/MC/AArch64/SME2/bfmul-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SME2/bfmul.s
create mode 100644 llvm/test/MC/AArch64/SME2/fmul-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SME2/fmul.s
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index b763aa15a7c3f1..76e0501a5cc233 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -1007,6 +1007,11 @@ let Predicates = [HasSME2p2] in {
defm BFMOP4A : sme2_bfmop4as_widening<0, "bfmop4a">;
defm BFMOP4S : sme2_bfmop4as_widening<1, "bfmop4s">;
+
+ defm FMUL_2ZZ : sme2_multi2_fmul_sm<"fmul">;
+ defm FMUL_2Z2Z : sme2_multi2_fmul_mm< "fmul">;
+ defm FMUL_4ZZ : sme2_multi4_fmul_sm<"fmul">;
+ defm FMUL_4Z4Z : sme2_multi4_fmul_mm< "fmul">;
} // [HasSME2p2]
let Predicates = [HasSME2p2, HasSMEB16B16] in {
@@ -1024,3 +1029,8 @@ let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
let Predicates = [HasSME2p2, HasSMEF16F16] in {
def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">;
} // [HasSME2p2, HasSMEF16F16]
+
+let Predicates = [HasSME2, HasSVEBFSCALE] in {
+ defm BFMUL : sme2_bfmul_single<"bfmul">;
+ defm BFMUL : sme2_bfmul_multi<"bfmul">;
+} //[HasSME2, HasSVEBFSCALE]
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 4cfe18eddf481c..a05c5206320f71 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -5225,3 +5225,113 @@ multiclass sme2_bfmop4as_widening<bit S, string mnemonic> {
// Multiple vectors
def _M2Z2Z_S : sme2_bf16_fp32_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>;
}
+
+class sme2_multi2_fmul_sm<bits<2> size, string mnemonic, RegisterOperand vector_ty, RegisterOperand zpr_ty>
+ : I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, zpr_ty:$Zm),
+ mnemonic, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]> {
+ bits<4> Zd;
+ bits<4> Zn;
+ bits<4> Zm;
+
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = size;
+ let Inst{21} = 0b1;
+ let Inst{20-17} = Zm;
+ let Inst{16-10} = 0b0111010;
+ let Inst{9-6} = Zn;
+ let Inst{5} = 0b0;
+ let Inst{4-1} = Zd;
+ let Inst{0} = 0b0;
+}
+
+multiclass sme2_multi2_fmul_sm<string mnemonic> {
+ def _H : sme2_multi2_fmul_sm<0b01, mnemonic, ZZ_h_mul_r, ZPR4b16>;
+ def _S : sme2_multi2_fmul_sm<0b10, mnemonic, ZZ_s_mul_r, ZPR4b32>;
+ def _D : sme2_multi2_fmul_sm<0b11, mnemonic, ZZ_d_mul_r, ZPR4b64>;
+}
+
+class sme2_multi4_fmul_sm<bits<2> size, string mnemonic, RegisterOperand vector_ty, RegisterOperand zpr_ty>
+ : I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, zpr_ty:$Zm),
+ mnemonic, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]> {
+ bits<3> Zd;
+ bits<3> Zn;
+ bits<4> Zm;
+
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = size;
+ let Inst{21} = 0b1;
+ let Inst{20-17} = Zm;
+ let Inst{16-10} = 0b1111010;
+ let Inst{9-7} = Zn;
+ let Inst{6-5} = 0b00;
+ let Inst{4-2} = Zd;
+ let Inst{1-0} = 0b00;
+}
+
+multiclass sme2_multi4_fmul_sm<string mnemonic> {
+ def _H : sme2_multi4_fmul_sm<0b01, mnemonic, ZZZZ_h_mul_r, ZPR4b16>;
+ def _S : sme2_multi4_fmul_sm<0b10, mnemonic, ZZZZ_s_mul_r, ZPR4b32>;
+ def _D : sme2_multi4_fmul_sm<0b11, mnemonic, ZZZZ_d_mul_r, ZPR4b64>;
+}
+
+multiclass sme2_bfmul_single<string mnemonic> {
+ def _2ZZ : sme2_multi2_fmul_sm<0b00, mnemonic, ZZ_h_mul_r, ZPR4b16>;
+ def _4ZZ : sme2_multi4_fmul_sm<0b00, mnemonic, ZZZZ_h_mul_r, ZPR4b16>;
+}
+
+class sme2_multi2_fmul_mm<bits<2> size, string mnemonic, RegisterOperand vector_ty>
+ : I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, vector_ty:$Zm),
+ mnemonic, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]> {
+ bits<4> Zd;
+ bits<4> Zn;
+ bits<4> Zm;
+
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = size;
+ let Inst{21} = 0b1;
+ let Inst{20-17} = Zm;
+ let Inst{16-10} = 0b0111001;
+ let Inst{9-6} = Zn;
+ let Inst{5} = 0b0;
+ let Inst{4-1} = Zd;
+ let Inst{0} = 0b0;
+}
+
+multiclass sme2_multi2_fmul_mm<string mnemonic> {
+ def _H : sme2_multi2_fmul_mm<0b01, mnemonic, ZZ_h_mul_r>;
+ def _S : sme2_multi2_fmul_mm<0b10, mnemonic, ZZ_s_mul_r>;
+ def _D : sme2_multi2_fmul_mm<0b11, mnemonic, ZZ_d_mul_r>;
+}
+
+class sme2_multi4_fmul_mm<bits<2> size, string mnemonic, RegisterOperand vector_ty>
+ : I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, vector_ty:$Zm),
+ mnemonic, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]> {
+ bits<3> Zd;
+ bits<3> Zn;
+ bits<3> Zm;
+
+ let Inst{31-24} = 0b11000001;
+ let Inst{23-22} = size;
+ let Inst{21} = 0b1;
+ let Inst{20-18} = Zm;
+ let Inst{17-10} = 0b01111001;
+ let Inst{9-7} = Zn;
+ let Inst{6-5} = 0b00;
+ let Inst{4-2} = Zd;
+ let Inst{1-0} = 0b00;
+}
+
+multiclass sme2_multi4_fmul_mm<string mnemonic> {
+ def _H : sme2_multi4_fmul_mm<0b01, mnemonic, ZZZZ_h_mul_r>;
+ def _S : sme2_multi4_fmul_mm<0b10, mnemonic, ZZZZ_s_mul_r>;
+ def _D : sme2_multi4_fmul_mm<0b11, mnemonic, ZZZZ_d_mul_r>;
+}
+
+multiclass sme2_bfmul_multi<string mnemonic> {
+ def _2Z2Z : sme2_multi2_fmul_mm<0b00, mnemonic, ZZ_h_mul_r>;
+ def _4Z4Z : sme2_multi4_fmul_mm<0b00, mnemonic, ZZZZ_h_mul_r>;
+}
diff --git a/llvm/test/MC/AArch64/SME2/bfmul-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmul-diagnostics.s
new file mode 100644
index 00000000000000..c28cc5cd426dda
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfmul-diagnostics.s
@@ -0,0 +1,111 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2,+sve-bfscale 2>&1 < %s| FileCheck %s
+
+// Multiple and single, 2 regs
+
+bfmul {z0.s-z1.s}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z1.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfmul {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z0.s-z1.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z1.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfmul {z0.h-z1.h}, {z0.h-z2.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+// Multiple and single, 4 regs
+
+bfmul {z0.s-z3.s}, {z0.h-z3.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z1.h-z4.h}, {z0.h-z3.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfmul {z0.h-z4.h}, {z0.h-z3.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfmul {z0.h-z3.h}, {z0.s-z3.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z3.h}, {z1.h-z4.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfmul {z0.h-z3.h}, {z0.h-z4.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+// Multiple, 2 regs
+
+bfmul {z0.s-z1.s}, {z0.h-z1.h}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z1.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfmul {z0.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z0.s-z1.s}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z1.h-z2.h}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfmul {z0.h-z1.h}, {z0.h-z2.h}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z1.h-z2.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z2.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+// Multiple, 4 regs
+
+bfmul {z0.s-z3.s}, {z0.h-z3.h}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z1.h-z4.h}, {z0.h-z3.h}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfmul {z0.h-z4.h}, {z0.h-z3.h}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfmul {z0.h-z3.h}, {z0.s-z3.s}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z3.h}, {z1.h-z4.h}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfmul {z0.h-z3.h}, {z0.h-z4.h}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z1.h-z4.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z4.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
diff --git a/llvm/test/MC/AArch64/SME2/bfmul.s b/llvm/test/MC/AArch64/SME2/bfmul.s
new file mode 100644
index 00000000000000..10a43848c73819
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfmul.s
@@ -0,0 +1,92 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2,+sve-bfscale - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sve-bfscale -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// Multiple and single, 2 regs
+
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h // 11000001-00100000-11101000-00000000
+// CHECK-INST: bfmul { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xe8,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c120e800 <unknown>
+
+bfmul {z20.h-z21.h}, {z10.h-z11.h}, z10.h // 11000001-00110100-11101001-01010100
+// CHECK-INST: bfmul { z20.h, z21.h }, { z10.h, z11.h }, z10.h
+// CHECK-ENCODING: [0x54,0xe9,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c134e954 <unknown>
+
+bfmul {z30.h-z31.h}, {z30.h-z31.h}, z15.h // 11000001-00111110-11101011-11011110
+// CHECK-INST: bfmul { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0xde,0xeb,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c13eebde <unknown>
+
+// Multiple and single, 4 regs
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h // 11000001-00100001-11101000-00000000
+// CHECK-INST: bfmul { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xe8,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c121e800 <unknown>
+
+bfmul {z20.h-z23.h}, {z8.h-z11.h}, z10.h // 11000001-00110101-11101001-00010100
+// CHECK-INST: bfmul { z20.h - z23.h }, { z8.h - z11.h }, z10.h
+// CHECK-ENCODING: [0x14,0xe9,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c135e914 <unknown>
+
+bfmul {z28.h-z31.h}, {z28.h-z31.h}, z15.h // 11000001-00111111-11101011-10011100
+// CHECK-INST: bfmul { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x9c,0xeb,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c13feb9c <unknown>
+
+// Multiple, 2 regs
+bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} // 11000001-00100000-11100100-00000000
+// CHECK-INST: bfmul { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xe4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c120e400 <unknown>
+
+bfmul {z20.h-z21.h}, {z10.h-z11.h}, {z20.h-z21.h} // 11000001-00110100-11100101-01010100
+// CHECK-INST: bfmul { z20.h, z21.h }, { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x54,0xe5,0x34,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c134e554 <unknown>
+
+bfmul {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h} // 11000001-00111110-11100111-11011110
+// CHECK-INST: bfmul { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xde,0xe7,0x3e,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c13ee7de <unknown>
+
+// Multiple, 4 regs
+
+bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} // 11000001-00100001-11100100-00000000
+// CHECK-INST: bfmul { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xe4,0x21,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c121e400 <unknown>
+
+bfmul {z20.h-z23.h}, {z8.h-z11.h}, {z20.h-z23.h} // 11000001-00110101-11100101-00010100
+// CHECK-INST: bfmul { z20.h - z23.h }, { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xe5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c135e514 <unknown>
+
+bfmul {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h} // 11000001-00111101-11100111-10011100
+// CHECK-INST: bfmul { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9c,0xe7,0x3d,0xc1]
+// CHECK-ERROR: instruction requires: sme2 sve-bfscale
+// CHECK-UNKNOWN: c13de79c <unknown>
diff --git a/llvm/test/MC/AArch64/SME2/fmul-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmul-diagnostics.s
new file mode 100644
index 00000000000000..2fdd3f82adc1dd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmul-diagnostics.s
@@ -0,0 +1,112 @@
+
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
+
+// Multiple and single, 2 regs
+
+fmul {z0.b-z1.b}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z1.s-z2.s}, {z0.s-z1.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+fmul {z0.d-z2.d}, {z0.d-z1.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.h-z1.h}, {z0.b-z1.b}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.s-z1.s}, {z1.s-z2.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+fmul {z0.d-z1.d}, {z0.d-z2.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.h-z1.h}, {z0.h-z1.h}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+fmul {z0.s-z1.s}, {z0.s-z1.s}, z16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z15.s
+
+// Multiple and single, 4 regs
+
+fmul {z0.b-z3.b}, {z0.h-z3.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z1.s-z3.s}, {z0.h-z3.h}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.d-z4.d}, {z0.d-z3.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+fmul {z0.h-z3.h}, {z0.b-z3.b}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.s-z3.s}, {z1.s-z3.s}, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.d-z3.d}, {z0.d-z4.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+fmul {z0.h-z3.h}, {z0.h-z3.h}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
+
+fmul {z0.s-z3.s}, {z0.s-z3.s}, z16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z15.s
+
+// Multiple, 2 regs
+
+fmul {z0.b-z1.b}, {z0.h-z1.h}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z1.s-z2.s}, {z0.s-z1.s}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+fmul {z0.d-z2.d}, {z0.d-z1.d}, {z0.d-z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.h-z1.h}, {z0.b-z1.b}, {z0.h-z1.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.s-z1.s}, {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+fmul {z0.d-z1.d}, {z0.d-z2.d}, {z0.d-z1.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.b-z1.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.s-z1.s}, {z0.s-z1.s}, {z1.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+
+fmul {z0.d-z1.d}, {z0.d-z1.d}, {z0.d-z2.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+// Multiple, 4 regs
+
+fmul {z0.b-z3.b}, {z0.h-z3.h}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z1.s-z3.s}, {z0.s-z3.s}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.d-z4.d}, {z0.d-z3.d}, {z0.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+fmul {z0.h-z3.h}, {z0.b-z3.b}, {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.s-z3.s}, {z1.s-z3.s}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.d-z3.d}, {z0.d-z4.d}, {z0.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+
+fmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.b-z3.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.s-z3.s}, {z0.s-z3.s}, {z1.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmul {z0.d-z3.d}, {z0.d-z3.d}, {z0.d-z4.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
diff --git a/llvm/test/MC/AArch64/SME2/fmul.s b/llvm/test/MC/AArch64/SME2/fmul.s
new file mode 100644
index 00000000000000..c5510000612522
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/fmul.s
@@ -0,0 +1,261 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// Multiple and single, 2 regs
+
+// 16-bit elements
+
+fmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h // 11000001-01100000-11101000-00000000
+// CHECK-INST: fmul { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xe8,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c160e800 <unknown>
+
+fmul {z20.h-z21.h}, {z10.h-z11.h}, z10.h // 11000001-01110100-11101001-01010100
+// CHECK-INST: fmul { z20.h, z21.h }, { z10.h, z11.h }, z10.h
+// CHECK-ENCODING: [0x54,0xe9,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c174e954 <unknown>
+
+fmul {z30.h-z31.h}, {z30.h-z31.h}, z15.h // 11000001-01111110-11101011-11011110
+// CHECK-INST: fmul { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0xde,0xeb,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c17eebde <unknown>
+
+// 32-bit elements
+
+fmul {z0.s-z1.s}, {z0.s-z1.s}, z0.s // 11000001-10100000-11101000-00000000
+// CHECK-INST: fmul { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xe8,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1a0e800 <unknown>
+
+fmul {z20.s-z21.s}, {z10.s-z11.s}, z10.s // 11000001-10110100-11101001-01010100
+// CHECK-INST: fmul { z20.s, z21.s }, { z10.s, z11.s }, z10.s
+// CHECK-ENCODING: [0x54,0xe9,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1b4e954 <unknown>
+
+fmul {z30.s-z31.s}, {z30.s-z31.s}, z15.s // 11000001-10111110-11101011-11011110
+// CHECK-INST: fmul { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0xde,0xeb,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1beebde <unknown>
+
+// 64-bit elements
+
+fmul {z0.d-z1.d}, {z0.d-z1.d}, z0.d // 11000001-11100000-11101000-00000000
+// CHECK-INST: fmul { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xe8,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1e0e800 <unknown>
+
+fmul {z20.d-z21.d}, {z10.d-z11.d}, z10.d // 11000001-11110100-11101001-01010100
+// CHECK-INST: fmul { z20.d, z21.d }, { z10.d, z11.d }, z10.d
+// CHECK-ENCODING: [0x54,0xe9,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1f4e954 <unknown>
+
+fmul {z30.d-z31.d}, {z30.d-z31.d}, z15.d // 11000001-11111110-11101011-11011110
+// CHECK-INST: fmul { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0xde,0xeb,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1feebde <unknown>
+
+// Multiple and single, 4 regs
+
+// 16-bit elements
+
+fmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h // 11000001-01100001-11101000-00000000
+// CHECK-INST: fmul { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xe8,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c161e800 <unknown>
+
+fmul {z20.h-z23.h}, {z8.h-z11.h}, z10.h // 11000001-01110101-11101001-00010100
+// CHECK-INST: fmul { z20.h - z23.h }, { z8.h - z11.h }, z10.h
+// CHECK-ENCODING: [0x14,0xe9,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c175e914 <unknown>
+
+fmul {z28.h-z31.h}, {z28.h-z31.h}, z15.h // 11000001-01111111-11101011-10011100
+// CHECK-INST: fmul { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x9c,0xeb,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c17feb9c <unknown>
+
+// 32-bit elements
+
+fmul {z0.s-z3.s}, {z0.s-z3.s}, z0.s // 11000001-10100001-11101000-00000000
+// CHECK-INST: fmul { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xe8,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1a1e800 <unknown>
+
+fmul {z20.s-z23.s}, {z8.s-z11.s}, z10.s // 11000001-10110101-11101001-00010100
+// CHECK-INST: fmul { z20.s - z23.s }, { z8.s - z11.s }, z10.s
+// CHECK-ENCODING: [0x14,0xe9,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1b5e914 <unknown>
+
+fmul {z28.s-z31.s}, {z28.s-z31.s}, z15.s // 11000001-10111111-11101011-10011100
+// CHECK-INST: fmul { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x9c,0xeb,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1bfeb9c <unknown>
+
+// 64-bit elements
+
+fmul {z0.d-z3.d}, {z0.d-z3.d}, z0.d // 11000001-11100001-11101000-00000000
+// CHECK-INST: fmul { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xe8,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1e1e800 <unknown>
+
+fmul {z20.d-z23.d}, {z8.d-z11.d}, z10.d // 11000001-11110101-11101001-00010100
+// CHECK-INST: fmul { z20.d - z23.d }, { z8.d - z11.d }, z10.d
+// CHECK-ENCODING: [0x14,0xe9,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1f5e914 <unknown>
+
+fmul {z28.d-z31.d}, {z28.d-z31.d}, z15.d // 11000001-11111111-11101011-10011100
+// CHECK-INST: fmul { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x9c,0xeb,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1ffeb9c <unknown>
+
+// Multiple, 2 regs
+
+// 16-bit elements
+
+fmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} // 11000001-01100000-11100100-00000000
+// CHECK-INST: fmul { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xe4,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c160e400 <unknown>
+
+fmul {z20.h-z21.h}, {z10.h-z11.h}, {z20.h-z21.h} // 11000001-01110100-11100101-01010100
+// CHECK-INST: fmul { z20.h, z21.h }, { z10.h, z11.h }, { z20.h, z21.h }
+// CHECK-ENCODING: [0x54,0xe5,0x74,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c174e554 <unknown>
+
+fmul {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h} // 11000001-01111110-11100111-11011110
+// CHECK-INST: fmul { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xde,0xe7,0x7e,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c17ee7de <unknown>
+
+// 32-bit elememnts
+
+fmul {z0.s-z1.s}, {z0.s-z1.s}, {z0.s-z1.s} // 11000001-10100000-11100100-00000000
+// CHECK-INST: fmul { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe4,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1a0e400 <unknown>
+
+fmul {z20.s-z21.s}, {z10.s-z11.s}, {z20.s-z21.s} // 11000001-10110100-11100101-01010100
+// CHECK-INST: fmul { z20.s, z21.s }, { z10.s, z11.s }, { z20.s, z21.s }
+// CHECK-ENCODING: [0x54,0xe5,0xb4,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1b4e554 <unknown>
+
+fmul {z30.s-z31.s}, {z30.s-z31.s}, {z30.s-z31.s} // 11000001-10111110-11100111-11011110
+// CHECK-INST: fmul { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xde,0xe7,0xbe,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1bee7de <unknown>
+
+// 64-bit elements
+
+fmul {z0.d-z1.d}, {z0.d-z1.d}, {z0.d-z1.d} // 11000001-11100000-11100100-00000000
+// CHECK-INST: fmul { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
+// CHECK-ENCODING: [0x00,0xe4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1e0e400 <unknown>
+
+fmul {z20.d-z21.d}, {z10.d-z11.d}, {z20.d-z21.d} // 11000001-11110100-11100101-01010100
+// CHECK-INST: fmul { z20.d, z21.d }, { z10.d, z11.d }, { z20.d, z21.d }
+// CHECK-ENCODING: [0x54,0xe5,0xf4,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1f4e554 <unknown>
+
+fmul {z30.d-z31.d}, {z30.d-z31.d}, {z30.d-z31.d} // 11000001-11111110-11100111-11011110
+// CHECK-INST: fmul { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
+// CHECK-ENCODING: [0xde,0xe7,0xfe,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1fee7de <unknown>
+
+// Multiple, 4 regs
+
+// 16-bit elements
+
+fmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} // 11000001-01100001-11100100-00000000
+// CHECK-INST: fmul { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xe4,0x61,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c161e400 <unknown>
+
+fmul {z20.h-z23.h}, {z8.h-z11.h}, {z20.h-z23.h} // 11000001-01110101-11100101-00010100
+// CHECK-INST: fmul { z20.h - z23.h }, { z8.h - z11.h }, { z20.h - z23.h }
+// CHECK-ENCODING: [0x14,0xe5,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c175e514 <unknown>
+
+fmul {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h} // 11000001-01111101-11100111-10011100
+// CHECK-INST: fmul { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9c,0xe7,0x7d,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c17de79c <unknown>
+
+// 32-bit elements
+
+fmul {z0.s-z3.s}, {z0.s-z3.s}, {z0.s-z3.s} // 11000001-10100001-11100100-00000000
+// CHECK-INST: fmul { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe4,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1a1e400 <unknown>
+
+fmul {z20.s-z23.s}, {z8.s-z11.s}, {z20.s-z23.s} // 11000001-10110101-11100101-00010100
+// CHECK-INST: fmul { z20.s - z23.s }, { z8.s - z11.s }, { z20.s - z23.s }
+// CHECK-ENCODING: [0x14,0xe5,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1b5e514 <unknown>
+
+fmul {z28.s-z31.s}, {z28.s-z31.s}, {z28.s-z31.s} // 11000001-10111101-11100111-10011100
+// CHECK-INST: fmul { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe7,0xbd,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1bde79c <unknown>
+
+// 64-bit elements
+
+fmul {z0.d-z3.d}, {z0.d-z3.d}, {z0.d-z3.d} // 11000001-11100001-11100100-00000000
+// CHECK-INST: fmul { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xe4,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1e1e400 <unknown>
+
+fmul {z20.d-z23.d}, {z8.d-z11.d}, {z20.d-z23.d} // 11000001-11110101-11100101-00010100
+// CHECK-INST: fmul { z20.d - z23.d }, { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x14,0xe5,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1f5e514 <unknown>
+
+fmul {z28.d-z31.d}, {z28.d-z31.d}, {z28.d-z31.d} // 11000001-11111101-11100111-10011100
+// CHECK-INST: fmul { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9c,0xe7,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2p2
+// CHECK-UNKNOWN: c1fde79c <unknown>
>From 000bac5a49714e8ed4f96c8e4e20137ccace39ac Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.concatto at arm.com>
Date: Thu, 24 Oct 2024 09:22:42 +0000
Subject: [PATCH 2/2] Move FMUL test to SME2p2 folder
---
llvm/test/MC/AArch64/{SME2 => SME2p2}/fmul-diagnostics.s | 0
llvm/test/MC/AArch64/{SME2 => SME2p2}/fmul.s | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename llvm/test/MC/AArch64/{SME2 => SME2p2}/fmul-diagnostics.s (100%)
rename llvm/test/MC/AArch64/{SME2 => SME2p2}/fmul.s (99%)
diff --git a/llvm/test/MC/AArch64/SME2/fmul-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmul-diagnostics.s
similarity index 100%
rename from llvm/test/MC/AArch64/SME2/fmul-diagnostics.s
rename to llvm/test/MC/AArch64/SME2p2/fmul-diagnostics.s
diff --git a/llvm/test/MC/AArch64/SME2/fmul.s b/llvm/test/MC/AArch64/SME2p2/fmul.s
similarity index 99%
rename from llvm/test/MC/AArch64/SME2/fmul.s
rename to llvm/test/MC/AArch64/SME2p2/fmul.s
index c5510000612522..ec6f523867cef5 100644
--- a/llvm/test/MC/AArch64/SME2/fmul.s
+++ b/llvm/test/MC/AArch64/SME2p2/fmul.s
@@ -5,7 +5,7 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
-// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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