[llvm] [AArch64] Add asssembly/disassembly for FMOP4{A, S} (widening, 2-way, FP16 to FP32) instructions (PR #113346)

[via llvm-commits]

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@@ -0,0 +1,243 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2 < %s 2>&1 | FileCheck %s
+
+// FMOP4A
+
+// Single vectors
+
+fmop4a za0.d, z0.h, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand
+
+fmop4a za4.s, z0.h, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+fmop4a za0.s, z0.d, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register
+
+fmop4a za0.s, z15.h, z16.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register
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SpencerAbson wrote:

It might be best to check for the whole error string (e.g, `expected even register in z0.h..z14.h`) when testing the restrictions we want from `ZPR16Mul2_Lo`, I'm not sure it appears in this file.

https://github.com/llvm/llvm-project/pull/113346