[llvm] [AMDGPU] Add Wave Reduce Intrinsics for i32 type (PR #111342)

[Pravin Jagtap via llvm-commits]

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@@ -4861,10 +4881,75 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
   Register DstReg = MI.getOperand(0).getReg();
   MachineBasicBlock *RetBB = nullptr;
   if (isSGPR) {
-    // These operations with a uniform value i.e. SGPR are idempotent.
-    // Reduced value will be same as given sgpr.
-    BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
-    RetBB = &BB;
+    switch(Opc){
+      case AMDGPU::S_MIN_U32:
+      case AMDGPU::S_MIN_I32:
+      case AMDGPU::S_MAX_U32:
+      case AMDGPU::S_MAX_I32:
+      case AMDGPU::S_AND_B32:
+      case AMDGPU::S_OR_B32:{
+        // Idempotent operations.
+        BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
+        RetBB = &BB;
+        break;
+      }
+      case AMDGPU::S_XOR_B32:
+      case AMDGPU::S_ADD_I32:
+      case AMDGPU::S_SUB_I32:{
+        const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass();
+        const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg);
+        Register ExecMask = MRI.createVirtualRegister(WaveMaskRegClass);
+        Register CountOfActiveLanesReg = MRI.createVirtualRegister(DstRegClass);
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pravinjagtap wrote:

Just `ActiveLanes` ? In general, you are mangling type in your variable names everywhere. we can avoid that.

https://github.com/llvm/llvm-project/pull/111342