[llvm] d3f70db - [X86][MC] Support instructions of MSR_IMM (#113524)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 27 21:59:54 PDT 2024
Author: Freddy Ye
Date: 2024-10-28T12:59:51+08:00
New Revision: d3f70db51cbc0876937d404e96fbda04df793bd4
URL: https://github.com/llvm/llvm-project/commit/d3f70db51cbc0876937d404e96fbda04df793bd4
DIFF: https://github.com/llvm/llvm-project/commit/d3f70db51cbc0876937d404e96fbda04df793bd4.diff
LOG: [X86][MC] Support instructions of MSR_IMM (#113524)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Added:
llvm/test/MC/Disassembler/X86/apx/msr-imm.txt
llvm/test/MC/Disassembler/X86/msrimm-64.txt
llvm/test/MC/X86/apx/msrimm-att.s
llvm/test/MC/X86/apx/msrimm-intel.s
llvm/test/MC/X86/msrimm-64-att.s
llvm/test/MC/X86/msrimm-64-intel.s
Modified:
llvm/docs/ReleaseNotes.md
llvm/lib/Target/X86/X86InstrSystem.td
Removed:
################################################################################
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 7c7e687e94749e..2580f09be3ad77 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -221,6 +221,8 @@ Changes to the X86 Backend
* Supported ISA of `SM4(EVEX)`.
+* Supported ISA of `MSR_IMM`.
+
Changes to the OCaml bindings
-----------------------------
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index e1573b37d4dc26..dc701f1afc915f 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -466,7 +466,10 @@ multiclass Urdwrmsr<Map rrmap, string suffix> {
"urdmsr\t{$imm, $dst|$dst, $imm}",
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
T_MAP7, VEX, XD, NoCD8;
-}
+ def RDMSRri#suffix : Ii32<0xf6, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "rdmsr\t{$imm, $dst|$dst, $imm}", []>,
+ T_MAP7, VEX, XD, NoCD8;
+ }
let mayStore = 1 in {
let OpMap = rrmap in
def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
@@ -476,6 +479,9 @@ multiclass Urdwrmsr<Map rrmap, string suffix> {
"uwrmsr\t{$src, $imm|$imm, $src}",
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
T_MAP7, VEX, XS, NoCD8;
+ def WRMSRNSir#suffix : Ii32<0xf6, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+ "wrmsrns\t{$src, $imm|$imm, $src}",
+ []>, T_MAP7, VEX, XS, NoCD8;
}
}
diff --git a/llvm/test/MC/Disassembler/X86/apx/msr-imm.txt b/llvm/test/MC/Disassembler/X86/apx/msr-imm.txt
new file mode 100644
index 00000000000000..63465bb7070ea8
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/msr-imm.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: rdmsr $123, %r9
+# INTEL: rdmsr r9, 123
+0x62,0xd7,0x7f,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: rdmsr $123, %r19
+# INTEL: rdmsr r19, 123
+0x62,0xff,0x7f,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: wrmsrns %r9, $123
+# INTEL: wrmsrns 123, r9
+0x62,0xd7,0x7e,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: wrmsrns %r19, $123
+# INTEL: wrmsrns 123, r19
+0x62,0xff,0x7e,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/msrimm-64.txt b/llvm/test/MC/Disassembler/X86/msrimm-64.txt
new file mode 100644
index 00000000000000..625d70d739cd34
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/msrimm-64.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: rdmsr $123, %r9
+# INTEL: rdmsr r9, 123
+0xc4,0xc7,0x7b,0xf6,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: wrmsrns %r9, $123
+# INTEL: wrmsrns 123, r9
+0xc4,0xc7,0x7a,0xf6,0xc1,0x7b,0x00,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/msrimm-att.s b/llvm/test/MC/X86/apx/msrimm-att.s
new file mode 100644
index 00000000000000..e4259f19cb7be4
--- /dev/null
+++ b/llvm/test/MC/X86/apx/msrimm-att.s
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+
+## rdmsr
+
+// CHECK: {evex} rdmsr $123, %r9
+// CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} rdmsr $123, %r9
+
+// CHECK: rdmsr $123, %r19
+// CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+ rdmsr $123, %r19
+
+## wrmsrns
+
+# CHECK: {evex} wrmsrns %r9, $123
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} wrmsrns %r9, $123
+
+# CHECK: wrmsrns %r19, $123
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+ wrmsrns %r19, $123
diff --git a/llvm/test/MC/X86/apx/msrimm-intel.s b/llvm/test/MC/X86/apx/msrimm-intel.s
new file mode 100644
index 00000000000000..d7eab047dd0cf7
--- /dev/null
+++ b/llvm/test/MC/X86/apx/msrimm-intel.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## urdmsr
+
+# CHECK: {evex} rdmsr r9, 123
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} rdmsr r9, 123
+
+# CHECK: rdmsr r19, 123
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+ rdmsr r19, 123
+
+## uwrmsr
+
+# CHECK: {evex} wrmsrns 123, r9
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} wrmsrns 123, r9
+
+# CHECK: wrmsrns 123, r19
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf6,0xc3,0x7b,0x00,0x00,0x00]
+ wrmsrns 123, r19
diff --git a/llvm/test/MC/X86/msrimm-64-att.s b/llvm/test/MC/X86/msrimm-64-att.s
new file mode 100644
index 00000000000000..e69eb7ff29a61e
--- /dev/null
+++ b/llvm/test/MC/X86/msrimm-64-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+// RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+// ERROR-COUNT-2: error:
+// ERROR-NOT: error:
+
+// CHECK: rdmsr $123, %r9
+// CHECK: encoding: [0xc4,0xc7,0x7b,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ rdmsr $123, %r9
+
+// CHECK: wrmsrns %r9, $123
+// CHECK: encoding: [0xc4,0xc7,0x7a,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ wrmsrns %r9, $123
+
diff --git a/llvm/test/MC/X86/msrimm-64-intel.s b/llvm/test/MC/X86/msrimm-64-intel.s
new file mode 100644
index 00000000000000..e1ae9c67912365
--- /dev/null
+++ b/llvm/test/MC/X86/msrimm-64-intel.s
@@ -0,0 +1,10 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: rdmsr r9, 123
+// CHECK: encoding: [0xc4,0xc7,0x7b,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ rdmsr r9, 123
+
+// CHECK: wrmsrns 123, r9
+// CHECK: encoding: [0xc4,0xc7,0x7a,0xf6,0xc1,0x7b,0x00,0x00,0x00]
+ wrmsrns 123, r9
+
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