[llvm] [RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (PR #113756)

[Craig Topper via llvm-commits]

topperc wrote:

> Is this still profitable even for cases when there's no shift needed, e.g. would a vsetvli be better than a single csrr?

CSR reads in general are seializing. Vlenb needs to be special cased in the microarchitecture. Some versions of SiFive cores missed this optimization. Have we checked BananaPi?

https://github.com/llvm/llvm-project/pull/113756