[llvm] [RegAlloc][RISCV] Increase the spill weight by target factor (PR #113675)

[Luke Lau via llvm-commits]

https://github.com/lukel97 commented:

Thanks for looking at this, I also tried this a few months ago, and saw the same test diff where we're able to remove a lot of LMUL 8 spills. 

However whilst it helps the in-tree tests a lot when I tried it out on SPEC CPU 2017 I got a 50% increase in spills generated overall, have you been able to check if you run into this too?

My approach also didn't use the reg class weight but instead I scaled the weight by the physical register size in bytes. From what I remember investigating the register class weight was related to register pressure calculation, which seemed orthogonal to spilling

https://github.com/llvm/llvm-project/pull/113675