[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

Peilin Ye via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 25 18:54:21 PDT 2024


================
@@ -703,6 +715,39 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
   return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
 }
 
+SDValue BPFTargetLowering::LowerATOMIC_LOAD(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  const char *Msg =
+      "sequentially consistent (seq_cst) atomic load is not supported";
+  SDNode *N = Op.getNode();
+  SDLoc DL(N);
+
+  if (cast<AtomicSDNode>(N)->getMergedOrdering() ==
+      AtomicOrdering::SequentiallyConsistent)
+    fail(DL, DAG, Msg);
+
+  return Op;
+}
+
+SDValue BPFTargetLowering::LowerATOMIC_STORE(SDValue Op,
+                                             SelectionDAG &DAG) const {
+  const char *Msg =
+      "sequentially consistent (seq_cst) atomic store is not supported";
+  EVT VT = Op.getOperand(1).getValueType();
+  SDNode *N = Op.getNode();
+  SDLoc DL(N);
+
+  // Promote operand #1 (value to store) if necessary.
+  if (!isTypeLegal(VT))
+    return SDValue();
----------------
peilin-ye wrote:

Ah!  I see, thanks!  So:
```diff
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -93,7 +93,7 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
   }
 
-  for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
+  for (auto VT : {MVT::i32, MVT::i64}) {
     setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
     setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
   }
@@ -737,10 +737,6 @@ SDValue BPFTargetLowering::LowerATOMIC_STORE(SDValue Op,
   SDNode *N = Op.getNode();
   SDLoc DL(N);
 
-  // Promote operand #1 (value to store) if necessary.
-  if (!isTypeLegal(VT))
-    return SDValue();
-
   if (cast<AtomicSDNode>(N)->getMergedOrdering() ==
       AtomicOrdering::SequentiallyConsistent)
     fail(DL, DAG, Msg);
```

https://github.com/llvm/llvm-project/pull/108636


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