[llvm] a0c3189 - [CodeGen][NFC] Properly split MachineLICM and EarlyMachineLICM (#113573)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 25 11:19:27 PDT 2024
Author: Gaëtan Bossu
Date: 2024-10-25T11:19:22-07:00
New Revision: a0c318938a528cfbef509a2516b36dd2411a52b6
URL: https://github.com/llvm/llvm-project/commit/a0c318938a528cfbef509a2516b36dd2411a52b6
DIFF: https://github.com/llvm/llvm-project/commit/a0c318938a528cfbef509a2516b36dd2411a52b6.diff
LOG: [CodeGen][NFC] Properly split MachineLICM and EarlyMachineLICM (#113573)
Both are based on MachineLICMBase, and the functionality there is
"switched" based on a PreRegAlloc flag. This commit is simply about
trusting the original value of that flag, defined by the `MachineLICM`
and `EarlyMachineLICM` classes.
The `PreRegAlloc` flag used to be overwritten it based on MRI.isSSA(),
which is un-reliable due to how it is inferred by the MIRParser. I see
that we can now define isSSA in MIR (thanks @gargaroff ), meaning the
fix isn’t really needed anymore, but redefining that flag still feels
wrong.
Note that I'm looking into upstreaming more changes to MachineLICM, see
[the discourse
thread](https://discourse.llvm.org/t/extending-post-regalloc-machinelicm/82725).
Added:
Modified:
llvm/lib/CodeGen/MachineLICM.cpp
llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
llvm/test/CodeGen/AMDGPU/licm-valu.mir
llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 793ad75759ccb8..7ea07862b839d0 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -391,12 +391,6 @@ bool MachineLICMImpl::run(MachineFunction &MF) {
MRI = &MF.getRegInfo();
SchedModel.init(&ST);
- // FIXME: Remove this assignment or convert to an assert? (dead variable PreRegAlloc)
- // MachineLICM and PostRAMachineLICM were distinguished by introducing
- // EarlyMachineLICM and MachineLICM respectively to avoid "using an unreliable
- // MRI::isSSA() check to determine whether register allocation has happened"
- // (See 4a7c8e7).
- PreRegAlloc = MRI->isSSA();
HasProfileData = MF.getFunction().hasProfileData();
if (PreRegAlloc)
diff --git a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
index 406025c4fde302..90ff68d30a3a0e 100644
--- a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
+++ b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
@@ -3,9 +3,6 @@
---
name: test
tracksRegLiveness: true
-isSSA: false
-registers:
- - { id: 0, class: gpr64 }
stack:
- { id: 0, size: 8, type: spill-slot }
body: |
@@ -30,14 +27,11 @@ body: |
bb.2:
liveins: $x0
- %0 = COPY $x0
...
+
---
name: test2
tracksRegLiveness: true
-isSSA: false
-registers:
- - { id: 0, class: gpr64 }
stack:
- { id: 0, size: 8, type: spill-slot }
body: |
@@ -62,5 +56,4 @@ body: |
bb.2:
liveins: $x0
- %0 = COPY $x0
...
diff --git a/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir b/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
index e63009fdcb43cf..dd478f94e1039e 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass machinelicm -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
# MachineLICM shall limit hoisting of V_CVT instructions out of the loop keeping
# register pressure within the budget. VGPR budget at occupancy 10 is 24 vgprs.
diff --git a/llvm/test/CodeGen/AMDGPU/licm-valu.mir b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
index b4f5e057f532b5..6a28eee19d503c 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-valu.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s
---
name: hoist_move
diff --git a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
index ff3d9ca378dbd5..135b14d6836a09 100644
--- a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
+++ b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-- -passes machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-- -passes early-machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
--- |
@x = dso_local global i32 0, align 4
@z = dso_local local_unnamed_addr global [1024 x i32] zeroinitializer, align 16
diff --git a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
index d4d59e14724ebe..b65a0e71af1dd2 100644
--- a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
@@ -1,6 +1,6 @@
--- |
- ; RUN: llc -run-pass=machinelicm -o - %s | FileCheck %s
- ; RUN: llc -passes=machinelicm -o - %s | FileCheck %s
+ ; RUN: llc -run-pass=early-machinelicm -o - %s | FileCheck %s
+ ; RUN: llc -passes=early-machinelicm -o - %s | FileCheck %s
; Line numbers should not be retained when loop invariant instructions are hoisted.
; Doing so causes poor stepping bevavior.
;
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