[llvm] [CostModel][LoopVectorize] Move some loop vectoriser tests (PR #113702)

David Sherwood via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 25 08:32:17 PDT 2024 

https://github.com/david-arm created https://github.com/llvm/llvm-project/pull/113702

Many tests that were in test/Analysis/CostModel were actually
loop vectoriser tests. I've moved them as follows:

Analysis/CostModel/X86 -> Transforms/LoopVectorize/X86/CostModel Analysis/CostModel/AArch64/arith-fp-frem.ll ->
  Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll

>From c266ab073c7f11bba583b18f845b5417fe967578 Mon Sep 17 00:00:00 2001
From: David Sherwood <david.sherwood at arm.com>
Date: Fri, 25 Oct 2024 15:28:06 +0000
Subject: [PATCH] [CostModel][LoopVectorize] Move some loop vectoriser tests

Many tests that were in test/Analysis/CostModel were actually
loop vectoriser tests. I've moved them as follows:

Analysis/CostModel/X86 -> Transforms/LoopVectorize/X86/CostModel
Analysis/CostModel/AArch64/arith-fp-frem.ll ->
  Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
---
 .../LoopVectorize/AArch64/arith-fp-frem-costs.ll}                 | 0
 .../LoopVectorize/X86/CostModel}/gather-i16-with-i8-index.ll      | 0
 .../LoopVectorize/X86/CostModel}/gather-i32-with-i8-index.ll      | 0
 .../LoopVectorize/X86/CostModel}/gather-i64-with-i8-index.ll      | 0
 .../LoopVectorize/X86/CostModel}/gather-i8-with-i8-index.ll       | 0
 .../X86/CostModel}/handle-iptr-with-data-layout-to-not-assert.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-2.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-3.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-4.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-5.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-6.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-7.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-8.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-2.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-3.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-4.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-5.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-6.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-7.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-8.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-half.ll         | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-2.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-3.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-4.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-5.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-6.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-7.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-8.ll | 0
 .../X86/CostModel}/interleaved-load-i32-stride-2-indices-0u.ll    | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-2.ll | 0
 .../X86/CostModel}/interleaved-load-i32-stride-3-indices-01u.ll   | 0
 .../X86/CostModel}/interleaved-load-i32-stride-3-indices-0uu.ll   | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-3.ll | 0
 .../X86/CostModel}/interleaved-load-i32-stride-4-indices-012u.ll  | 0
 .../X86/CostModel}/interleaved-load-i32-stride-4-indices-01uu.ll  | 0
 .../X86/CostModel}/interleaved-load-i32-stride-4-indices-0uuu.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-4.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-5.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-6.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-7.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-8.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-2.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-3.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-4.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-5.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-6.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-7.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-8.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-2.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-3.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-4.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-5.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-6.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-7.ll  | 0
 .../LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-8.ll  | 0
 .../X86/CostModel}/interleaved-store-f32-stride-2.ll              | 0
 .../X86/CostModel}/interleaved-store-f32-stride-3.ll              | 0
 .../X86/CostModel}/interleaved-store-f32-stride-4.ll              | 0
 .../X86/CostModel}/interleaved-store-f32-stride-5.ll              | 0
 .../X86/CostModel}/interleaved-store-f32-stride-6.ll              | 0
 .../X86/CostModel}/interleaved-store-f32-stride-7.ll              | 0
 .../X86/CostModel}/interleaved-store-f32-stride-8.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-2.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-3.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-4.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-5.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-6.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-7.ll              | 0
 .../X86/CostModel}/interleaved-store-f64-stride-8.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-2.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-3.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-4.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-5.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-6.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-7.ll              | 0
 .../X86/CostModel}/interleaved-store-i16-stride-8.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-2.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-3.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-4.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-5.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-6.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-7.ll              | 0
 .../X86/CostModel}/interleaved-store-i32-stride-8.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-2.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-3.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-4.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-5.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-6.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-7.ll              | 0
 .../X86/CostModel}/interleaved-store-i64-stride-8.ll              | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-2.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-3.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-4.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-5.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-6.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-7.ll | 0
 .../LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-8.ll | 0
 .../X86/CostModel}/masked-gather-i32-with-i8-index.ll             | 0
 .../X86/CostModel}/masked-gather-i64-with-i8-index.ll             | 0
 .../LoopVectorize/X86/CostModel}/masked-interleaved-load-i16.ll   | 0
 .../LoopVectorize/X86/CostModel}/masked-interleaved-store-i16.ll  | 0
 .../LoopVectorize/X86/CostModel}/masked-load-i16.ll               | 0
 .../LoopVectorize/X86/CostModel}/masked-load-i32.ll               | 0
 .../LoopVectorize/X86/CostModel}/masked-load-i64.ll               | 0
 .../LoopVectorize/X86/CostModel}/masked-load-i8.ll                | 0
 .../X86/CostModel}/masked-scatter-i32-with-i8-index.ll            | 0
 .../X86/CostModel}/masked-scatter-i64-with-i8-index.ll            | 0
 .../LoopVectorize/X86/CostModel}/masked-store-i16.ll              | 0
 .../LoopVectorize/X86/CostModel}/masked-store-i32.ll              | 0
 .../LoopVectorize/X86/CostModel}/masked-store-i64.ll              | 0
 .../LoopVectorize/X86/CostModel}/masked-store-i8.ll               | 0
 .../LoopVectorize/X86/CostModel}/scatter-i16-with-i8-index.ll     | 0
 .../LoopVectorize/X86/CostModel}/scatter-i32-with-i8-index.ll     | 0
 .../LoopVectorize/X86/CostModel}/scatter-i64-with-i8-index.ll     | 0
 .../LoopVectorize/X86/CostModel}/scatter-i8-with-i8-index.ll      | 0
 .../LoopVectorize/X86/CostModel}/strided-load-i16.ll              | 0
 .../LoopVectorize/X86/CostModel}/strided-load-i32.ll              | 0
 .../LoopVectorize/X86/CostModel}/strided-load-i64.ll              | 0
 .../LoopVectorize/X86/CostModel}/strided-load-i8.ll               | 0
 119 files changed, 0 insertions(+), 0 deletions(-)
 rename llvm/test/{Analysis/CostModel/AArch64/arith-fp-frem.ll => Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll} (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/gather-i16-with-i8-index.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/gather-i32-with-i8-index.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/gather-i64-with-i8-index.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/gather-i8-with-i8-index.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/handle-iptr-with-data-layout-to-not-assert.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f32-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-f64-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-half.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i16-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-2-indices-0u.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-3-indices-01u.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-3-indices-0uu.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-4-indices-012u.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-4-indices-01uu.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-4-indices-0uuu.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i32-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i64-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-load-i8-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f32-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-f64-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i16-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i32-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-4.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-5.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-6.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-7.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i64-stride-8.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-2.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-3.ll (100%)
 rename llvm/test/{Analysis/CostModel/X86 => Transforms/LoopVectorize/X86/CostModel}/interleaved-store-i8-stride-4.ll (100%)
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diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll
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diff --git a/llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
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diff --git a/llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
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diff --git a/llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll
diff --git a/llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll
diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/masked-store-i16.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/masked-store-i32.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/masked-store-i64.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/masked-store-i8.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll
diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll
diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll
diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll
diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i16.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i32.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i64.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
similarity index 100%
rename from llvm/test/Analysis/CostModel/X86/strided-load-i8.ll
rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll

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