[llvm] [AArch64] Do adc(s) machine instruction combine (PR #113663)

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git-clang-format --diff 786db636b9b6967087685a62af665046621b4957 4721f44511c50ee6c3ae35ce427b38f6710903f1 --extensions h,cpp -- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index bbb30c14b8..71ac050536 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -7022,7 +7022,6 @@ AArch64InstrInfo::getCombinerObjective(unsigned Pattern) const {
   }
 }
 
-
 /// Find instructions that can be turned into adc or adcs.
 /// CINC  I=A,CS
 /// ADD|S R,I,B or ADD|S R,B,I
@@ -7075,7 +7074,6 @@ static bool getAdcPatterns(MachineInstr &Root,
   return Found;
 }
 
-
 /// Return true when there is potentially a faster code sequence for an
 /// instruction chain ending in \p Root. All potential patterns are listed in
 /// the \p Pattern vector. Pattern should be sorted in priority order since the

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https://github.com/llvm/llvm-project/pull/113663