[llvm] [CodeGen] Avoid sinking vector comparisons during CodeGenPrepare (PR #113158)

[Jay Foad via llvm-commits]

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@@ -2389,7 +2389,7 @@ class TargetLoweringBase {
                                                EVT VT) const {
     // If a target has multiple condition registers, then it likely has logical
     // operations on those registers.
-    if (hasMultipleConditionRegisters())
+    if (hasMultiplePredicateRegisters(VT))
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jayfoad wrote:

>From looking at the use of this hook in `DAGCombiner::visitSELECT`, I think VT here is the type of X and Y. But `hasMultiplePredicateRegisters` should be passed the type of the predicate, which is hard coded to `MVT::i1`. (Please double check this since I find it quite confusing!)

https://github.com/llvm/llvm-project/pull/113158