[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

[Peilin Ye via llvm-commits]

================
@@ -48,6 +48,13 @@ def BPF_END  : BPFArithOp<0xd>;
 def BPF_XCHG    : BPFArithOp<0xe>;
 def BPF_CMPXCHG : BPFArithOp<0xf>;
 
+class BPFAtomicLoadStoreOp<bits<4> val> {
+  bits<4> Value = val;
+}
+
+def BPF_LOAD_ACQ : BPFAtomicLoadStoreOp<0x1>;
+def BPF_STORE_REL : BPFAtomicLoadStoreOp<0xb>;
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peilin-ye wrote:

@yonghong-song, my thinking was:

Right now for `BPF_ATOMIC` insns, we use a subset of `BPFArithOp<>` in `imm`:
```
def BPF_ADD  : BPFArithOp<0x0>;
def BPF_OR   : BPFArithOp<0x4>;
def BPF_AND  : BPFArithOp<0x5>;
def BPF_XOR  : BPFArithOp<0xa>;
def BPF_XCHG    : BPFArithOp<0xe>;
def BPF_CMPXCHG : BPFArithOp<0xf>;
```
Will we ever want to support other `BPFArithOp<>` ops in `BPF_ATOMIC` ?  Like, `0x1` is `BPF_SUB`, but it looks like currently atomic SUB is implemented using NEG + ADD:
```
    // atomic_load_sub can be represented as a neg followed
    // by an atomic_load_add.
```
So I thought, "OK, if we don't need to reserve `0x1` for `BPF_SUB`, then I can use it".  Similarly, `0xb` is `BPF_MOV` (moving value between registers), and I think it's safe to say we'll never need it for `BPF_ATOMIC`.

But `0x2` is `BPF_MUL`; will we ever support atomic multiplication? :-)
- - -
Am I overthinking this?  Should I simply use `0x1` and `0x2` ?

https://github.com/llvm/llvm-project/pull/108636