[llvm] [AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (PR #113634)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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git-clang-format --diff 8aa69a0d02e99e50db0242f75a192b1c2d826528 8559f96c65ae32cdcf65ad2f3a9bd184c011c39a --extensions cpp -- llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 795e1cca23..0f43096235 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -364,17 +364,17 @@ static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
 }
 
 static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm,
-                                           uint64_t /*Addr*/,
-                                           const MCDisassembler *Decoder) {
-   assert(isUInt<10>(Imm) && "10-bit encoding expected");
-
-   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
-   if (Imm & AMDGPU::EncValues::IS_VGPR) {
-     bool IsHi = Imm & (1 << 9);
-     unsigned RegIdx = Imm & 0xff;
-     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
-   }
-   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
+                                          uint64_t /*Addr*/,
+                                          const MCDisassembler *Decoder) {
+  assert(isUInt<10>(Imm) && "10-bit encoding expected");
+
+  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  if (Imm & AMDGPU::EncValues::IS_VGPR) {
+    bool IsHi = Imm & (1 << 9);
+    unsigned RegIdx = Imm & 0xff;
+    return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
+  }
+  return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
                                                    Imm & 0xFF, false, 0));
 }
 

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https://github.com/llvm/llvm-project/pull/113634