[llvm] [CodeGen] Avoid sinking vector comparisons during CodeGenPrepare (PR #113158)

[via llvm-commits]

goldsteinn wrote:

> > > Alternatively, I could also introduce a TLI hook to query the
> > > target if this is a preferred solution?
> > 
> > 
> > This seems pretty similiar to existing `shouldNormalizeToSelectSequence` or `hasMultipleConditionRegisters`. Maybe `shouldNormalizeToSelectSequence` should become `shouldSinkComparisons` more generally (whether it be into selects or BBs).
> 
> Hmm, it looks like `shouldNormalizeToSelectSequence` is a virtual function overridden by AArch64 and is used by the DAGCombiner for a different problem. It looks like changing this function would be beyond the scope of this patch, however I am happy to investigate this as a follow-on if that's ok? Is the idea to avoid performing the DAG combine too if for vector comparisons the target has multiple vector predicate registers?

Sure, moreso what I meant was it seems we essentially have 2 existing flags that are related to avoiding transforms targeting single-predicate cmp ISAs. If you do choose to add a flags, it probably should co-opt or replace one of those.

https://github.com/llvm/llvm-project/pull/113158