[llvm] [AArch64] Add assembly/disassembly for SVE zeroing int-float conversions (PR #113605)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 24 11:17:26 PDT 2024
https://github.com/SpencerAbson created https://github.com/llvm/llvm-project/pull/113605
This patch adds assembly/disassembly for the following predicated SVE2.2 instructions
- SCVTF (zeroing)
- UCVTF (zeroing)
- FCVTZS (zeroing)
- FCVTZU (zeroing)
- FLOGB (zeroing)
- In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
>From 88e5029b61d303f3af3ce54bd3255c7c8591dd28 Mon Sep 17 00:00:00 2001
From: Spencer Abson <Spencer.Abson at arm.com>
Date: Thu, 24 Oct 2024 17:49:28 +0000
Subject: [PATCH] [AArch64] Add assembly/disassembly for zeroing SVE int-float
cvts
Add assembly/disassembly for the following SVE2.2 instructions
- SCVTF (zeroing)
- UCVTF (zeroing)
- FCVTZS (zeroing)
- FCVTZU (zeroing)
- FLOGB (zeroing)
---
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 9 +++
llvm/lib/Target/AArch64/SVEInstrFormats.td | 26 ++++++++
llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s | 2 +-
.../MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s | 34 ++++++++++
llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s | 63 +++++++++++++++++++
.../MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s | 34 ++++++++++
llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s | 63 +++++++++++++++++++
.../MC/AArch64/SVE2p2/flogb_z-diagnostics.s | 47 ++++++++++++++
llvm/test/MC/AArch64/SVE2p2/flogb_z.s | 33 ++++++++++
.../MC/AArch64/SVE2p2/scvtf_z-diagnostics.s | 34 ++++++++++
llvm/test/MC/AArch64/SVE2p2/scvtf_z.s | 63 +++++++++++++++++++
.../MC/AArch64/SVE2p2/ucvtf_z-diagnostics.s | 34 ++++++++++
llvm/test/MC/AArch64/SVE2p2/ucvtf_z.s | 63 +++++++++++++++++++
13 files changed, 504 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/flogb_z-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/flogb_z.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/scvtf_z-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/scvtf_z.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/ucvtf_z-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/SVE2p2/ucvtf_z.s
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 59859cb7442d59..bf6e25438633c7 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4227,6 +4227,15 @@ let Predicates = [HasSVE2p2orSME2p2] in {
// SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
+ // Floating-point convert to integer, zeroing predicate
+ defm FCVTZS_ZPzZ : sve_fp_z2op_p_zd_d<0b0, "fcvtzs">;
+ defm FCVTZU_ZPzZ : sve_fp_z2op_p_zd_d<0b1, "fcvtzu">;
+ // Integer convert to floating-point, zeroing predicate
+ defm SCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b0, "scvtf">;
+ defm UCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b1, "ucvtf">;
+ // Signed integer base 2 logarithm of fp value, zeroing predicate
+ defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">;
+
// Floating point round to integral fp value in integer size range
// Merging
defm FRINT32Z_ZPmZ : sve_fp_2op_p_zd_frint<0b00, "frint32z">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index fc2e889d3a1a03..af5c96eb5c8c56 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -3181,6 +3181,32 @@ multiclass sve_fp_z2op_p_zd_frint<bits<2> opc, string asm> {
def _D : sve_fp_z2op_p_zd<{ 0b0010, opc{1}, 1, opc{0} }, asm, ZPR64, ZPR64>;
}
+multiclass sve_fp_z2op_p_zd_d<bit U, string asm> {
+ def _HtoH : sve_fp_z2op_p_zd<{ 0b011101, U }, asm, ZPR16, ZPR16>;
+ def _HtoS : sve_fp_z2op_p_zd<{ 0b011110, U }, asm, ZPR16, ZPR32>;
+ def _HtoD : sve_fp_z2op_p_zd<{ 0b011111, U }, asm, ZPR16, ZPR64>;
+ def _StoS : sve_fp_z2op_p_zd<{ 0b101110, U }, asm, ZPR32, ZPR32>;
+ def _StoD : sve_fp_z2op_p_zd<{ 0b111110, U }, asm, ZPR32, ZPR64>;
+ def _DtoS : sve_fp_z2op_p_zd<{ 0b111100, U }, asm, ZPR64, ZPR32>;
+ def _DtoD : sve_fp_z2op_p_zd<{ 0b111111, U }, asm, ZPR64, ZPR64>;
+}
+
+multiclass sve_fp_z2op_p_zd_c<bit U, string asm> {
+ def _HtoH : sve_fp_z2op_p_zd<{ 0b011001, U }, asm, ZPR16, ZPR16>;
+ def _StoH : sve_fp_z2op_p_zd<{ 0b011010, U }, asm, ZPR32, ZPR16>;
+ def _StoS : sve_fp_z2op_p_zd<{ 0b101010, U }, asm, ZPR32, ZPR32>;
+ def _StoD : sve_fp_z2op_p_zd<{ 0b111000, U }, asm, ZPR32, ZPR64>;
+ def _DtoS : sve_fp_z2op_p_zd<{ 0b111010, U }, asm, ZPR64, ZPR32>;
+ def _DtoH : sve_fp_z2op_p_zd<{ 0b011011, U }, asm, ZPR64, ZPR16>;
+ def _DtoD : sve_fp_z2op_p_zd<{ 0b111011, U }, asm, ZPR64, ZPR64>;
+}
+
+multiclass sve_fp_z2op_p_zd_d_flogb<string asm> {
+ def _H : sve_fp_z2op_p_zd<0b0011001, asm, ZPR16, ZPR16>;
+ def _S : sve_fp_z2op_p_zd<0b0011010, asm, ZPR32, ZPR32>;
+ def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Integer Arithmetic - Binary Predicated Group
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s b/llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s
index ddb8c4ff35b6a3..60d9f9e5e242d5 100644
--- a/llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s
@@ -14,7 +14,7 @@ flogb z0.b, p0/m, z0.b
// Invalid predicate operation
flogb z0.s, p0/z, z0.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
// CHECK-NEXT: flogb z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s
new file mode 100644
index 00000000000000..1408cba4070bf4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
+
+fcvtzs z0.h, p0/z, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzs z0.h, p0/z, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcvtzs z0.h, p0/z, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzs z0.h, p0/z, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fcvtzs z0.h, p8/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fcvtzs z0.h, p8/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+fcvtzs z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: fcvtzs z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+fcvtzs z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: fcvtzs z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s b/llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s
new file mode 100644
index 00000000000000..a37f83c0f97b7c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s
@@ -0,0 +1,63 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// convert from half
+
+fcvtzs z0.h, p0/z, z0.h // 01100100-01011110-11000000-00000000
+// CHECK-INST: fcvtzs z0.h, p0/z, z0.h
+// CHECK-ENCODING: [0x00,0xc0,0x5e,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645ec000 <unknown>
+
+fcvtzs z23.s, p3/z, z13.h // 01100100-01011111-10001101-10110111
+// CHECK-INST: fcvtzs z23.s, p3/z, z13.h
+// CHECK-ENCODING: [0xb7,0x8d,0x5f,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645f8db7 <unknown>
+
+fcvtzs z31.d, p7/z, z31.h // 01100100-01011111-11011111-11111111
+// CHECK-INST: fcvtzs z31.d, p7/z, z31.h
+// CHECK-ENCODING: [0xff,0xdf,0x5f,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645fdfff <unknown>
+
+// convert from single
+
+fcvtzs z0.s, p0/z, z0.s // 01100100-10011111-10000000-00000000
+// CHECK-INST: fcvtzs z0.s, p0/z, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x9f,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 649f8000 <unknown>
+
+fcvtzs z21.d, p5/z, z10.s // 01100100-11011111-10010101-01010101
+// CHECK-INST: fcvtzs z21.d, p5/z, z10.s
+// CHECK-ENCODING: [0x55,0x95,0xdf,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64df9555 <unknown>
+
+// convert from double
+
+fcvtzs z23.s, p3/z, z13.d // 01100100-11011110-10001101-10110111
+// CHECK-INST: fcvtzs z23.s, p3/z, z13.d
+// CHECK-ENCODING: [0xb7,0x8d,0xde,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64de8db7 <unknown>
+
+fcvtzs z31.d, p7/z, z31.d // 01100100-11011111-11011111-11111111
+// CHECK-INST: fcvtzs z31.d, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xdf,0xdf,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dfdfff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s
new file mode 100644
index 00000000000000..fc4ecda82bd200
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
+
+fcvtzu z0.h, p0/z, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzu z0.h, p0/z, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fcvtzu z0.h, p0/z, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fcvtzu z0.h, p0/z, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fcvtzu z0.h, p8/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fcvtzu z0.h, p8/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+fcvtzu z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: fcvtzu z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+fcvtzu z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: fcvtzu z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s b/llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s
new file mode 100644
index 00000000000000..df1ac4016689b7
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s
@@ -0,0 +1,63 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// convert from half
+
+fcvtzu z0.h, p0/z, z0.h // 01100100-01011110-11100000-00000000
+// CHECK-INST: fcvtzu z0.h, p0/z, z0.h
+// CHECK-ENCODING: [0x00,0xe0,0x5e,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645ee000 <unknown>
+
+fcvtzu z21.s, p5/z, z10.h // 01100100-01011111-10110101-01010101
+// CHECK-INST: fcvtzu z21.s, p5/z, z10.h
+// CHECK-ENCODING: [0x55,0xb5,0x5f,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645fb555 <unknown>
+
+fcvtzu z23.d, p3/z, z13.h // 01100100-01011111-11101101-10110111
+// CHECK-INST: fcvtzu z23.d, p3/z, z13.h
+// CHECK-ENCODING: [0xb7,0xed,0x5f,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645fedb7 <unknown>
+
+// convert from single
+
+fcvtzu z21.s, p5/z, z10.s // 01100100-10011111-10110101-01010101
+// CHECK-INST: fcvtzu z21.s, p5/z, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x9f,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 649fb555 <unknown>
+
+fcvtzu z31.d, p7/z, z31.s // 01100100-11011111-10111111-11111111
+// CHECK-INST: fcvtzu z31.d, p7/z, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0xdf,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dfbfff <unknown>
+
+// convert from double
+
+fcvtzu z0.s, p0/z, z0.d // 01100100-11011110-10100000-00000000
+// CHECK-INST: fcvtzu z0.s, p0/z, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xde,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dea000 <unknown>
+
+fcvtzu z31.d, p7/z, z31.d // 01100100-11011111-11111111-11111111
+// CHECK-INST: fcvtzu z31.d, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xff,0xdf,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dfffff <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/flogb_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/flogb_z-diagnostics.s
new file mode 100644
index 00000000000000..8fd528e1fc05d4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/flogb_z-diagnostics.s
@@ -0,0 +1,47 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+flogb z0.b, p0/z, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: flogb z0.b, p0/z, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+flogb z0.h, p0/z, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: flogb z0.h, p0/z, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+flogb z0.s, p0/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: flogb z0.s, p0/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+flogb z0.d, p0/z, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: flogb z0.d, p0/z, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+flogb z0.h, p8/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: flogb z0.h, p8/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+flogb z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: flogb z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+flogb z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: flogb z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/flogb_z.s b/llvm/test/MC/AArch64/SVE2p2/flogb_z.s
new file mode 100644
index 00000000000000..1b056aa928ce23
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/flogb_z.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+flogb z0.h, p0/z, z0.h // 01100100-00011110-10100000-00000000
+// CHECK-INST: flogb z0.h, p0/z, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x1e,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 641ea000 <unknown>
+
+flogb z23.s, p3/z, z13.s // 01100100-00011110-11001101-10110111
+// CHECK-INST: flogb z23.s, p3/z, z13.s
+// CHECK-ENCODING: [0xb7,0xcd,0x1e,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 641ecdb7 <unknown>
+
+flogb z31.d, p7/z, z31.d // 01100100-00011110-11111111-11111111
+// CHECK-INST: flogb z31.d, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xff,0x1e,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 641effff <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/scvtf_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/scvtf_z-diagnostics.s
new file mode 100644
index 00000000000000..9dd08927146259
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/scvtf_z-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
+
+scvtf z0.s, p0/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: scvtf z0.s, p0/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+scvtf z0.d, p0/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: scvtf z0.d, p0/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+scvtf z0.h, p8/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: scvtf z0.h, p8/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+scvtf z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: scvtf z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+scvtf z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: scvtf z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p2/scvtf_z.s b/llvm/test/MC/AArch64/SVE2p2/scvtf_z.s
new file mode 100644
index 00000000000000..b8898c6485f619
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/scvtf_z.s
@@ -0,0 +1,63 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// convert to half
+
+scvtf z0.h, p0/z, z0.h // 01100100-01011100-11000000-00000000
+// CHECK-INST: scvtf z0.h, p0/z, z0.h
+// CHECK-ENCODING: [0x00,0xc0,0x5c,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645cc000 <unknown>
+
+scvtf z21.h, p5/z, z10.s // 01100100-01011101-10010101-01010101
+// CHECK-INST: scvtf z21.h, p5/z, z10.s
+// CHECK-ENCODING: [0x55,0x95,0x5d,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645d9555 <unknown>
+
+scvtf z31.h, p7/z, z31.d // 01100100-01011101-11011111-11111111
+// CHECK-INST: scvtf z31.h, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xdf,0x5d,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645ddfff <unknown>
+
+// convert to single
+
+scvtf z0.s, p0/z, z0.s // 01100100-10011101-10000000-00000000
+// CHECK-INST: scvtf z0.s, p0/z, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x9d,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 649d8000 <unknown>
+
+scvtf z23.s, p3/z, z13.d // 01100100-11011101-10001101-10110111
+// CHECK-INST: scvtf z23.s, p3/z, z13.d
+// CHECK-ENCODING: [0xb7,0x8d,0xdd,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dd8db7 <unknown>
+
+// convert to double
+
+scvtf z21.d, p5/z, z10.s // 01100100-11011100-10010101-01010101
+// CHECK-INST: scvtf z21.d, p5/z, z10.s
+// CHECK-ENCODING: [0x55,0x95,0xdc,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dc9555 <unknown>
+
+scvtf z31.d, p7/z, z31.d // 01100100-11011101-11011111-11111111
+// CHECK-INST: scvtf z31.d, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xdf,0xdd,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dddfff <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/ucvtf_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/ucvtf_z-diagnostics.s
new file mode 100644
index 00000000000000..1317428dafde03
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/ucvtf_z-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
+
+ucvtf z0.s, p0/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ucvtf z0.s, p0/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ucvtf z0.d, p0/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ucvtf z0.d, p0/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+ucvtf z0.h, p8/z, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ucvtf z0.h, p8/z, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+ucvtf z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: ucvtf z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+ucvtf z0.d, p0/z, z3.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: ucvtf z0.d, p0/z, z3.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p2/ucvtf_z.s b/llvm/test/MC/AArch64/SVE2p2/ucvtf_z.s
new file mode 100644
index 00000000000000..9e87afd60b4055
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p2/ucvtf_z.s
@@ -0,0 +1,63 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
+// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// convert to half
+
+ucvtf z0.h, p0/z, z0.h // 01100100-01011100-11100000-00000000
+// CHECK-INST: ucvtf z0.h, p0/z, z0.h
+// CHECK-ENCODING: [0x00,0xe0,0x5c,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645ce000 <unknown>
+
+ucvtf z21.h, p5/z, z10.s // 01100100-01011101-10110101-01010101
+// CHECK-INST: ucvtf z21.h, p5/z, z10.s
+// CHECK-ENCODING: [0x55,0xb5,0x5d,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645db555 <unknown>
+
+ucvtf z31.h, p7/z, z31.d // 01100100-01011101-11111111-11111111
+// CHECK-INST: ucvtf z31.h, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xff,0x5d,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 645dffff <unknown>
+
+// convert to single
+
+ucvtf z23.s, p3/z, z13.s // 01100100-10011101-10101101-10110111
+// CHECK-INST: ucvtf z23.s, p3/z, z13.s
+// CHECK-ENCODING: [0xb7,0xad,0x9d,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 649dadb7 <unknown>
+
+ucvtf z21.s, p5/z, z10.d // 01100100-11011101-10110101-01010101
+// CHECK-INST: ucvtf z21.s, p5/z, z10.d
+// CHECK-ENCODING: [0x55,0xb5,0xdd,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64ddb555 <unknown>
+
+// convert to double
+
+ucvtf z0.d, p0/z, z0.s // 01100100-11011100-10100000-00000000
+// CHECK-INST: ucvtf z0.d, p0/z, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0xdc,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64dca000 <unknown>
+
+ucvtf z31.d, p7/z, z31.d // 01100100-11011101-11111111-11111111
+// CHECK-INST: ucvtf z31.d, p7/z, z31.d
+// CHECK-ENCODING: [0xff,0xff,0xdd,0x64]
+// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
+// CHECK-UNKNOWN: 64ddffff <unknown>
\ No newline at end of file
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