[llvm] [AMDGPU][True16][MC] support more VOP3 inst in true16/fake16 format (PR #113603)

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``````````bash
git-clang-format --diff a4ace3de1b390451ce5e41bce74b90dcd992ab61 38a2b6a8cee8709aa97ba03a57e225ec5075e537 --extensions cpp -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 57b4268367..4f8ff074fe 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7417,24 +7417,24 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
   case AMDGPU::S_MINIMUM_F16:
   case AMDGPU::S_MAXIMUM_F16: {
     const DebugLoc &DL = Inst.getDebugLoc();
-      Register NewDst;
-      if (ST.useRealTrue16Insts())
-        NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
-      else
-        NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-      MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
-                                   .addImm(0) // src0_modifiers
-                                   .add(Inst.getOperand(1))
-                                   .addImm(0) // src1_modifiers
-                                   .add(Inst.getOperand(2))
-                                   .addImm(0)  // clamp
-                                   .addImm(0)  // omod
-                                   .addImm(0); // opsel0
-      MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
-      legalizeOperands(*NewInstr, MDT);
-      addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
-      Inst.eraseFromParent();
-      return;
+    Register NewDst;
+    if (ST.useRealTrue16Insts())
+      NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+    else
+      NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
+                                 .addImm(0) // src0_modifiers
+                                 .add(Inst.getOperand(1))
+                                 .addImm(0) // src1_modifiers
+                                 .add(Inst.getOperand(2))
+                                 .addImm(0)  // clamp
+                                 .addImm(0)  // omod
+                                 .addImm(0); // opsel0
+    MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
+    legalizeOperands(*NewInstr, MDT);
+    addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
+    Inst.eraseFromParent();
+    return;
   }
   }
 

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https://github.com/llvm/llvm-project/pull/113603