[llvm] [AArch64] Add @llvm.experimental.vector.match (PR #101974)

[David Sherwood via llvm-commits]

================
@@ -4041,6 +4041,30 @@ bool AArch64TTIImpl::isLegalToVectorizeReduction(
   }
 }
 
+bool AArch64TTIImpl::hasVectorMatch(VectorType *VT, unsigned SearchSize) const {
+  // Check that (i) the target has SVE2 and SVE is available, (ii) `VT' is a
+  // legal type for MATCH, and (iii) the search vector can be broadcast
+  // efficently to a legal type.
+  //
+  // Currently, we require the length of the search vector to match the minimum
+  // number of elements of `VT'. In practice this means we only support the
+  // cases (nxv16i8, 16), (v16i8, 16), (nxv8i16, 8), and (v8i16, 8), where the
+  // first element of the tuples corresponds to the type of the first argument
+  // and the second the length of the search vector.
+  //
+  // In the future we can support more cases. For example, (nxv16i8, 4) could
+  // be efficiently supported by using a DUP.S to broadcast the search
+  // elements, and more exotic cases like (nxv16i8, 5) could be supported by a
+  // sequence of SEL(DUP).
+  if (ST->hasSVE2() && ST->isSVEAvailable() &&
----------------
david-arm wrote:

Can you simplify this a bit more by removing some of the calls? For example,

```
  unsigned MinEC = VT->getElementCount().getKnownMinValue();
  if ((MinEC == 8 || MinEC == 16) &&
      VT->getPrimitiveSizeInBits().getKnownMinValue() == 128 &&
      (MinEC == SearchSize || (MinEC / 2) == SearchSize))
```

https://github.com/llvm/llvm-project/pull/101974