[llvm] [AArch64] Add assembly/disassembly for PMLAL/PMULL instructions (PR #113564)

[Jonathan Thackray via llvm-commits]

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@@ -3928,6 +3928,10 @@ let Predicates = [HasSVEAES2, HasSVE2p1orSSVE_AES] in {
   def AESD_4ZZI_B    : sve_crypto_binary_multi4<0b0100, "aesd">;
   def AESEMC_4ZZI_B  : sve_crypto_binary_multi4<0b1000, "aesemc">;
   def AESDMIC_4ZZI_B : sve_crypto_binary_multi4<0b1100, "aesdimc">;
+
+  // SVE_AES2 mutlti-vector polynomial multitply
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jthackray wrote:

typo:
```suggestion
  // SVE_AES2 mutlti-vector polynomial multiply
```

https://github.com/llvm/llvm-project/pull/113564