[llvm] [AArch64][SVE] Lower scalar FP converts to SVE when Neon is unavailable (PR #112564)

[Benjamin Maxwell via llvm-commits]

MacDue wrote:

> To clarify my previous comment. I'm not suggesting you "must" implement a set of `fp_op->gpr->fpr` combines specific to the sequences you care about. I only used that to illustrate my view of this being a combine rather than a lowering problem. If splitting the operation in two (i.e. in_place_fp_cvt->transfer_to_gpr) is sufficient for your needs (because there is already code that'll remove transfer_to_gpr) then that is preferable as the simplest solution that has the widest coverage.

Right, I've moved the logic here into `performIntToFpCombine()`/`performFpToIntCombine()` rather than having it in the lowerings, and that achieves the same goals (with the inserts/extracts generally folding away). 

> It is worth investigating a route where existing ISD nodes are used but with vector types. This could be the way to represent in_place_fp_cvt, which has the advantage of being generic but it's possible existing DACombines would undo the transformation. If that happens then at least we've a good reason to go the target specific ISD nodes route.

I'm not sure I follow :sweat_smile:, this is using the existing ISD nodes + insert/extract element. The AArch64 target nodes only come in after `LowerToPredicatedOp()`. 


https://github.com/llvm/llvm-project/pull/112564