[llvm] [RISCV] Allow crypto features to imply dependents (PR #112659)

[via llvm-commits]

workingjubilee wrote:

According to the ISA spec so far, Zvkt doesn't imply *any* instructions. It thus doesn't imply that any register state must be addressable, either. It just specifies that other instructions should be modified in behavior if they are executed. Thus, perversely, Zvkt could be implemented on a processor that implements zero of the instructions that Zvkt modifies.

https://github.com/llvm/llvm-project/pull/112659