[llvm] [LoongArch] Enable FeatureExtLSX for generic-la64 processor (PR #113421)

[WÁNG Xuěruì via llvm-commits]

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@@ -6,16 +6,10 @@
 define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
 ; CHECK-LABEL: callee_float_in_regs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi.d $sp, $sp, -16
-; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT:    st.d $fp, $sp, 0 # 8-byte Folded Spill
-; CHECK-NEXT:    move $fp, $a0
-; CHECK-NEXT:    move $a0, $a1
-; CHECK-NEXT:    bl %plt(__fixsfdi)
-; CHECK-NEXT:    add.d $a0, $fp, $a0
-; CHECK-NEXT:    ld.d $fp, $sp, 0 # 8-byte Folded Reload
-; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
-; CHECK-NEXT:    addi.d $sp, $sp, 16
+; CHECK-NEXT:    movgr2fr.w $fa0, $a1
+; CHECK-NEXT:    ftintrz.l.s $fa0, $fa0
+; CHECK-NEXT:    movfr2gr.d $a1, $fa0
+; CHECK-NEXT:    add.d $a0, $a0, $a1
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xen0n wrote:

The LP64S tests require updating of compilation flags so it stays soft-float.

https://github.com/llvm/llvm-project/pull/113421