[llvm] [AArch64] Add support for Armv9.6-A FEAT_SPE_EXC and FEAT_TRBE_EXC (PR #113463)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 23 07:37:30 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mc
Author: James Westwood (jwestwood921)
<details>
<summary>Changes</summary>
Add support for the following Armv9.6-A architecture extensions:
* FEAT_SPE_EXC - Statistical Profiling Extension profiling exceptions
* FEAT_TRBE_EXC - Trace Buffer Management Events profiling exceptions
as documented here:
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension
---
Full diff: https://github.com/llvm/llvm-project/pull/113463.diff
5 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+13)
- (added) llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s (+19)
- (added) llvm/test/MC/AArch64/armv9.6a-trbe-exception.s (+15)
- (added) llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt (+15)
- (added) llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt (+15)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1d2bb1d732346c..052cdf9e939265 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2048,3 +2048,16 @@ let Requires = [{ {AArch64::FeaturePCDPHINT} }] in {
// v9.6a Realm management extension enhancements
def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;
+
+// v9.6a Statistical Profiling Extension exception registers (FEAT_SPE_EXC)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PMBMAR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b101>;
+def : RWSysReg<"PMBSR_EL12", 0b11, 0b101, 0b1001, 0b1010, 0b011>;
+def : RWSysReg<"PMBSR_EL2", 0b11, 0b100, 0b1001, 0b1010, 0b011>;
+def : RWSysReg<"PMBSR_EL3", 0b11, 0b110, 0b1001, 0b1010, 0b011>;
+
+// v9.6a Trace Buffer Management Events exception registers (FEAT_TRBE_EXC)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"TRBSR_EL12", 0b11, 0b101, 0b1001, 0b1011, 0b011>;
+def : RWSysReg<"TRBSR_EL2", 0b11, 0b100, 0b1001, 0b1011, 0b011>;
+def : RWSysReg<"TRBSR_EL3", 0b11, 0b110, 0b1001, 0b1011, 0b011>;
diff --git a/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s b/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s
new file mode 100644
index 00000000000000..2314c414d4d96a
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s
@@ -0,0 +1,19 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s
+
+ msr pmbmar_el1, x0
+ msr pmbsr_el12, x0
+ msr pmbsr_el2, x0
+ msr pmbsr_el3, x0
+// CHECK: msr PMBMAR_EL1, x0 // encoding: [0xa0,0x9a,0x18,0xd5]
+// CHECK: msr PMBSR_EL12, x0 // encoding: [0x60,0x9a,0x1d,0xd5]
+// CHECK: msr PMBSR_EL2, x0 // encoding: [0x60,0x9a,0x1c,0xd5]
+// CHECK: msr PMBSR_EL3, x0 // encoding: [0x60,0x9a,0x1e,0xd5]
+
+ mrs x0, pmbmar_el1
+ mrs x0, pmbsr_el12
+ mrs x0, pmbsr_el2
+ mrs x0, pmbsr_el3
+// CHECK: mrs x0, PMBMAR_EL1 // encoding: [0xa0,0x9a,0x38,0xd5]
+// CHECK: mrs x0, PMBSR_EL12 // encoding: [0x60,0x9a,0x3d,0xd5]
+// CHECK: mrs x0, PMBSR_EL2 // encoding: [0x60,0x9a,0x3c,0xd5]
+// CHECK: mrs x0, PMBSR_EL3 // encoding: [0x60,0x9a,0x3e,0xd5]
diff --git a/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s b/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s
new file mode 100644
index 00000000000000..a8ba7c442e4ce4
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s
+
+ msr trbsr_el12, x0
+ msr trbsr_el2, x0
+ msr trbsr_el3, x0
+// CHECK: msr TRBSR_EL12, x0 // encoding: [0x60,0x9b,0x1d,0xd5]
+// CHECK: msr TRBSR_EL2, x0 // encoding: [0x60,0x9b,0x1c,0xd5]
+// CHECK: msr TRBSR_EL3, x0 // encoding: [0x60,0x9b,0x1e,0xd5]
+
+ mrs x0, trbsr_el12
+ mrs x0, trbsr_el2
+ mrs x0, trbsr_el3
+// CHECK: mrs x0, TRBSR_EL12 // encoding: [0x60,0x9b,0x3d,0xd5]
+// CHECK: mrs x0, TRBSR_EL2 // encoding: [0x60,0x9b,0x3c,0xd5]
+// CHECK: mrs x0, TRBSR_EL3 // encoding: [0x60,0x9b,0x3e,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt
new file mode 100644
index 00000000000000..446e2f0eb05c4e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+[0x60,0x9a,0x1d,0xd5]
+# CHECK: msr PMBSR_EL12, x0
+[0x60,0x9a,0x1c,0xd5]
+# CHECK: msr PMBSR_EL2, x0
+[0x60,0x9a,0x1e,0xd5]
+# CHECK: msr PMBSR_EL3, x0
+
+[0x60,0x9a,0x3d,0xd5]
+# CHECK: mrs x0, PMBSR_EL12
+[0x60,0x9a,0x3c,0xd5]
+# CHECK: mrs x0, PMBSR_EL2
+[0x60,0x9a,0x3e,0xd5]
+# CHECK: mrs x0, PMBSR_EL3
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt
new file mode 100644
index 00000000000000..4b39e107538d96
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+[0x60,0x9b,0x1d,0xd5]
+# CHECK: msr TRBSR_EL12, x0
+[0x60,0x9b,0x1c,0xd5]
+# CHECK: msr TRBSR_EL2, x0
+[0x60,0x9b,0x1e,0xd5]
+# CHECK: msr TRBSR_EL3, x0
+
+[0x60,0x9b,0x3d,0xd5]
+# CHECK: mrs x0, TRBSR_EL12
+[0x60,0x9b,0x3c,0xd5]
+# CHECK: mrs x0, TRBSR_EL2
+[0x60,0x9b,0x3e,0xd5]
+# CHECK: mrs x0, TRBSR_EL3
``````````
</details>
https://github.com/llvm/llvm-project/pull/113463
More information about the llvm-commits
mailing list