[llvm] [AArch64]Add convert and multiply-add SIMD&FP assembly/disassembly in… (PR #113296)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 23 04:21:06 PDT 2024
https://github.com/CarolineConcatto updated https://github.com/llvm/llvm-project/pull/113296
>From 061c9658d84c4d79fc18ab843d5c8c8c3131e766 Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.concatto at arm.com>
Date: Tue, 22 Oct 2024 10:27:04 +0000
Subject: [PATCH] [AArch64]Add convert and multiply-add SIMD&FP
assembly/disassembly instructions
This patch adds the following instructions:
Conversion between floating-point and integer:
FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU}
{S,U}CVTF
Advanced SIMD three-register extension:
FMMLA
According to https://developer.arm.com/documentation/ddi0602
Co-authored-by: Marian Lukac marian.lukac at arm.com
Co-authored-by: Spencer Abson spencer.abson at arm.com
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 109 ++++++--
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 25 +-
llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s | 46 ++++
llvm/test/MC/AArch64/FP8/fmmla.s | 25 ++
llvm/test/MC/AArch64/armv9.6a-cvtf.s | 61 +++++
llvm/test/MC/AArch64/armv9.6a-fcvt.s | 253 ++++++++++++++++++
.../test/MC/AArch64/directive-arch-negative.s | 18 ++
llvm/test/MC/AArch64/directive-arch.s | 12 +
.../directive-arch_extension-negative.s | 20 +-
.../MC/AArch64/directive-arch_extension.s | 12 +
llvm/test/MC/AArch64/directive-cpu.s | 12 +
llvm/test/MC/AArch64/neon-diagnostics.s | 108 +++++---
12 files changed, 638 insertions(+), 63 deletions(-)
create mode 100644 llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/FP8/fmmla.s
create mode 100644 llvm/test/MC/AArch64/armv9.6a-cvtf.s
create mode 100644 llvm/test/MC/AArch64/armv9.6a-fcvt.s
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 4b24b166143dca..cc727ae0d48de6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -5005,6 +5005,32 @@ multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
}
}
+multiclass FPToIntegerSIMDScalar<bits<2> rmode, bits<3> opcode, string asm> {
+ // double-precision to 32-bit SIMD/FPR
+ def SDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, FPR32, asm,
+ []> {
+ let Inst{31} = 0; // 32-bit FPR flag
+ }
+
+ // half-precision to 32-bit SIMD/FPR
+ def SHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, FPR32, asm,
+ []> {
+ let Inst{31} = 0; // 32-bit FPR flag
+ }
+
+ // half-precision to 64-bit SIMD/FPR
+ def DHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, FPR64, asm,
+ []> {
+ let Inst{31} = 1; // 64-bit FPR flag
+ }
+
+ // single-precision to 64-bit SIMD/FPR
+ def DSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, FPR64, asm,
+ []> {
+ let Inst{31} = 1; // 64-bit FPR flag
+ }
+}
+
multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
SDPatternOperator OpN> {
// Scaled half-precision to 32-bit
@@ -5066,7 +5092,7 @@ multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
//---
let mayStore = 0, mayLoad = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
-class BaseIntegerToFP<bit isUnsigned,
+class BaseIntegerToFP<bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType,
Operand immType, string asm, list<dag> pattern>
: I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
@@ -5076,15 +5102,16 @@ class BaseIntegerToFP<bit isUnsigned,
bits<5> Rn;
bits<6> scale;
let Inst{30-24} = 0b0011110;
- let Inst{21-17} = 0b00001;
- let Inst{16} = isUnsigned;
+ let Inst{21} = 0b0;
+ let Inst{20-19} = rmode;
+ let Inst{18-16} = opcode;
let Inst{15-10} = scale;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}
let mayRaiseFPException = 1, Uses = [FPCR] in
-class BaseIntegerToFPUnscaled<bit isUnsigned,
+class BaseIntegerToFPUnscaled<bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType,
ValueType dvt, string asm, SDPatternOperator node>
: I<(outs dstType:$Rd), (ins srcType:$Rn),
@@ -5094,49 +5121,50 @@ class BaseIntegerToFPUnscaled<bit isUnsigned,
bits<5> Rn;
bits<6> scale;
let Inst{30-24} = 0b0011110;
- let Inst{21-17} = 0b10001;
- let Inst{16} = isUnsigned;
+ let Inst{21} = 0b1;
+ let Inst{20-19} = rmode;
+ let Inst{18-16} = opcode;
let Inst{15-10} = 0b000000;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
}
-multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
+multiclass IntegerToFP<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator node> {
// Unscaled
- def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
+ def UWHri: BaseIntegerToFPUnscaled<rmode, opcode, GPR32, FPR16, f16, asm, node> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{23-22} = 0b11; // 16-bit FPR flag
let Predicates = [HasFullFP16];
}
- def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
+ def UWSri: BaseIntegerToFPUnscaled<rmode, opcode, GPR32, FPR32, f32, asm, node> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
- def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
+ def UWDri: BaseIntegerToFPUnscaled<rmode, opcode, GPR32, FPR64, f64, asm, node> {
let Inst{31} = 0; // 32-bit GPR flag
let Inst{23-22} = 0b01; // 64-bit FPR flag
}
- def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
+ def UXHri: BaseIntegerToFPUnscaled<rmode, opcode, GPR64, FPR16, f16, asm, node> {
let Inst{31} = 1; // 64-bit GPR flag
let Inst{23-22} = 0b11; // 16-bit FPR flag
let Predicates = [HasFullFP16];
}
- def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
+ def UXSri: BaseIntegerToFPUnscaled<rmode, opcode, GPR64, FPR32, f32, asm, node> {
let Inst{31} = 1; // 64-bit GPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
- def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
+ def UXDri: BaseIntegerToFPUnscaled<rmode, opcode, GPR64, FPR64, f64, asm, node> {
let Inst{31} = 1; // 64-bit GPR flag
let Inst{23-22} = 0b01; // 64-bit FPR flag
}
// Scaled
- def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_recip_f16_i32, asm,
+ def SWHri: BaseIntegerToFP<rmode, opcode, GPR32, FPR16, fixedpoint_recip_f16_i32, asm,
[(set (f16 FPR16:$Rd),
(fmul (node GPR32:$Rn),
fixedpoint_recip_f16_i32:$scale))]> {
@@ -5146,7 +5174,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let Predicates = [HasFullFP16];
}
- def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_recip_f32_i32, asm,
+ def SWSri: BaseIntegerToFP<rmode, opcode, GPR32, FPR32, fixedpoint_recip_f32_i32, asm,
[(set FPR32:$Rd,
(fmul (node GPR32:$Rn),
fixedpoint_recip_f32_i32:$scale))]> {
@@ -5155,7 +5183,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let scale{5} = 1;
}
- def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_recip_f64_i32, asm,
+ def SWDri: BaseIntegerToFP<rmode, opcode, GPR32, FPR64, fixedpoint_recip_f64_i32, asm,
[(set FPR64:$Rd,
(fmul (node GPR32:$Rn),
fixedpoint_recip_f64_i32:$scale))]> {
@@ -5164,7 +5192,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let scale{5} = 1;
}
- def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_recip_f16_i64, asm,
+ def SXHri: BaseIntegerToFP<rmode, opcode, GPR64, FPR16, fixedpoint_recip_f16_i64, asm,
[(set (f16 FPR16:$Rd),
(fmul (node GPR64:$Rn),
fixedpoint_recip_f16_i64:$scale))]> {
@@ -5173,7 +5201,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let Predicates = [HasFullFP16];
}
- def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_recip_f32_i64, asm,
+ def SXSri: BaseIntegerToFP<rmode, opcode, GPR64, FPR32, fixedpoint_recip_f32_i64, asm,
[(set FPR32:$Rd,
(fmul (node GPR64:$Rn),
fixedpoint_recip_f32_i64:$scale))]> {
@@ -5181,7 +5209,7 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
- def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_recip_f64_i64, asm,
+ def SXDri: BaseIntegerToFP<rmode, opcode, GPR64, FPR64, fixedpoint_recip_f64_i64, asm,
[(set FPR64:$Rd,
(fmul (node GPR64:$Rn),
fixedpoint_recip_f64_i64:$scale))]> {
@@ -5190,6 +5218,32 @@ multiclass IntegerToFP<bit isUnsigned, string asm, SDPatternOperator node> {
}
}
+multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator node = null_frag> {
+ // 32-bit to half-precision
+ def HSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR16, f16, asm, node> {
+ let Inst{31} = 0; // 32-bit FPR flag
+ let Inst{23-22} = 0b11; // 16-bit FPR flag
+ }
+
+ // 32-bit to double-precision
+ def DSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR64, f64, asm, node> {
+ let Inst{31} = 0; // 32-bit FPR flag
+ let Inst{23-22} = 0b01; // 64-bit FPR flag
+ }
+
+ // 64-bit to half-precision
+ def HDr: BaseIntegerToFPUnscaled<rmode, opcode, FPR64, FPR16, f16, asm, node> {
+ let Inst{31} = 1; // 64-bit FPR flag
+ let Inst{23-22} = 0b11; // 16-bit FPR flag
+ }
+
+ // 64-bit to single-precision
+ def SDr: BaseIntegerToFPUnscaled<rmode, opcode, FPR64, FPR32, f32, asm, node> {
+ let Inst{31} = 1; // 64-bit FPR flag
+ let Inst{23-22} = 0b00; // 16-bit FPR flag
+ }
+}
+
//---
// Unscaled integer <-> floating point conversion (i.e. FMOV)
//---
@@ -12687,3 +12741,20 @@ multiclass AtomicFPStore<bit R, bits<3> op0, string asm> {
def S : BaseAtomicFPStore<FPR32, 0b10, R, op0, asm>;
def H : BaseAtomicFPStore<FPR16, 0b01, R, op0, asm>;
}
+
+class BaseSIMDThreeSameVectorFP8MatrixMul<string asm, bits<2> size, string kind>
+ : BaseSIMDThreeSameVectorTied<1, 1, {size, 0}, 0b11101,
+ V128, asm, ".16b", []> {
+ let AsmString = !strconcat(asm, "{\t$Rd", kind, ", $Rn", ".16b",
+ ", $Rm", ".16b", "}");
+}
+
+multiclass SIMDThreeSameVectorFP8MatrixMul<string asm>{
+ def v8f16: BaseSIMDThreeSameVectorFP8MatrixMul<asm, 0b00, ".8h">{
+ let Predicates = [HasNEON, HasF8F16MM];
+ }
+ def v4f32: BaseSIMDThreeSameVectorFP8MatrixMul<asm, 0b10, ".4s">{
+ let Predicates = [HasNEON, HasF8F32MM];
+ }
+}
+
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 4bd36e9eacbc68..67ce6733da36dc 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4710,6 +4710,19 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
+let Predicates = [HasNEON, HasFPRCVT] in{
+ defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas">;
+ defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau">;
+ defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms">;
+ defm FCVTMU : FPToIntegerSIMDScalar<0b10, 0b101, "fcvtmu">;
+ defm FCVTNS : FPToIntegerSIMDScalar<0b01, 0b010, "fcvtns">;
+ defm FCVTNU : FPToIntegerSIMDScalar<0b01, 0b011, "fcvtnu">;
+ defm FCVTPS : FPToIntegerSIMDScalar<0b10, 0b010, "fcvtps">;
+ defm FCVTPU : FPToIntegerSIMDScalar<0b10, 0b011, "fcvtpu">;
+ defm FCVTZS : FPToIntegerSIMDScalar<0b10, 0b110, "fcvtzs">;
+ defm FCVTZU : FPToIntegerSIMDScalar<0b10, 0b111, "fcvtzu">;
+}
+
// AArch64's FCVT instructions saturate when out of range.
multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {
let Predicates = [HasFullFP16] in {
@@ -4868,8 +4881,13 @@ def : Pat<(i64 (any_llround f64:$Rn)),
// Scaled integer to floating point conversion instructions.
//===----------------------------------------------------------------------===//
-defm SCVTF : IntegerToFP<0, "scvtf", any_sint_to_fp>;
-defm UCVTF : IntegerToFP<1, "ucvtf", any_uint_to_fp>;
+defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>;
+defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>;
+
+let Predicates = [HasNEON, HasFPRCVT] in {
+ defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf">;
+ defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf">;
+}
def : Pat<(f16 (fdiv (f16 (any_sint_to_fp (i32 GPR32:$Rn))), fixedpoint_f16_i32:$scale)),
(SCVTFSWHri GPR32:$Rn, fixedpoint_f16_i32:$scale)>;
@@ -10371,6 +10389,9 @@ let Predicates = [HasLSFE] in {
def STBFMINNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b111, "stbfminnml">;
}
+let Uses = [FPMR, FPCR] in
+defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla">;
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
diff --git a/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s b/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
new file mode 100644
index 00000000000000..cf8d216581240a
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s
@@ -0,0 +1,46 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+f8f16mm,+f8f32mm 2>&1 < %s| FileCheck %s
+
+fmmla v0.4h, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.4h, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.8s, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
+// CHECK-NEXT: fmmla v0.8s, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.4s, v1.4s, v2.4s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.4s, v1.4s, v2.4s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.8h, v1.8h, v2.8h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.8h, v1.8h, v2.8h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.16b, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.16b, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.d, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.d, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.2d, v1.16b, v2.16b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.2d, v1.16b, v2.16b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.8h, v1.8b, v2.8b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.8h, v1.8b, v2.8b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmmla v0.4s, v1.8b, v2.8b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmmla v0.4s, v1.8b, v2.8b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/FP8/fmmla.s b/llvm/test/MC/AArch64/FP8/fmmla.s
new file mode 100644
index 00000000000000..922f4c9d918ce9
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/fmmla.s
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | llvm-objdump -d --mattr=+f8f16mm,+f8f32mm - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=-f8f16mm,-f8f32mm - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f8f16mm,+f8f32mm < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+f8f16mm,+f8f32mm -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+fmmla v0.8h, v1.16b, v2.16b
+// CHECK-INST: fmmla v0.8h, v1.16b, v2.16b
+// CHECK-ENCODING: [0x20,0xec,0x02,0x6e]
+// CHECK-ERROR: instruction requires: f8f16mm
+// CHECK-UNKNOWN: 6e02ec20 <unknown>
+
+fmmla v0.4s, v1.16b, v2.16b
+// CHECK-INST: fmmla v0.4s, v1.16b, v2.16b
+// CHECK-ENCODING: [0x20,0xec,0x82,0x6e]
+// CHECK-ERROR: instruction requires: f8f32mm
+// CHECK-UNKNOWN: 6e82ec20 <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/armv9.6a-cvtf.s b/llvm/test/MC/AArch64/armv9.6a-cvtf.s
new file mode 100644
index 00000000000000..6858d3896af5ab
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-cvtf.s
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --mattr=+fprcvt - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=-fprcvt - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+fprcvt -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+scvtf d1, s2
+// CHECK-INST: scvtf d1, s2
+// CHECK-ENCODING: [0x41,0x00,0x7c,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7c0041 <unknown>
+
+scvtf h1, s2
+// CHECK-INST: scvtf h1, s2
+// CHECK-ENCODING: [0x41,0x00,0xfc,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efc0041 <unknown>
+
+scvtf h2, d0
+// CHECK-INST: scvtf h2, d0
+// CHECK-ENCODING: [0x02,0x00,0xfc,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efc0002 <unknown>
+
+scvtf s3, d4
+// CHECK-INST: scvtf s3, d4
+// CHECK-ENCODING: [0x83,0x00,0x3c,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3c0083 <unknown>
+
+ucvtf d1, s2
+// CHECK-INST: ucvtf d1, s2
+// CHECK-ENCODING: [0x41,0x00,0x7d,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7d0041 <unknown>
+
+ucvtf h1, s2
+// CHECK-INST: ucvtf h1, s2
+// CHECK-ENCODING: [0x41,0x00,0xfd,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efd0041 <unknown>
+
+ucvtf h2, d0
+// CHECK-INST: ucvtf h2, d0
+// CHECK-ENCODING: [0x02,0x00,0xfd,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efd0002 <unknown>
+
+ucvtf s3, d4
+// CHECK-INST: ucvtf s3, d4
+// CHECK-ENCODING: [0x83,0x00,0x3d,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3d0083 <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/armv9.6a-fcvt.s b/llvm/test/MC/AArch64/armv9.6a-fcvt.s
new file mode 100644
index 00000000000000..b14ec93563f5c4
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.6a-fcvt.s
@@ -0,0 +1,253 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --mattr=+fprcvt - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fprcvt < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=-fprcvt - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fprcvt < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+fprcvt -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+fcvtas s0, d1
+// CHECK-INST: fcvtas s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x7a,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7a0020 <unknown>
+
+fcvtas s1, h2
+// CHECK-INST: fcvtas s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xfa,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efa0041 <unknown>
+
+fcvtas d3, h4
+// CHECK-INST: fcvtas d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xfa,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efa0083 <unknown>
+
+fcvtas d0, s5
+// CHECK-INST: fcvtas d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x3a,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3a00a0 <unknown>
+
+fcvtau s0, d1
+// CHECK-INST: fcvtau s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x7b,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e7b0020 <unknown>
+
+fcvtau s1, h2
+// CHECK-INST: fcvtau s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xfb,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1efb0041 <unknown>
+
+fcvtau d3, h4
+// CHECK-INST: fcvtau d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xfb,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9efb0083 <unknown>
+
+fcvtau d0, s5
+// CHECK-INST: fcvtau d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x3b,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3b00a0 <unknown>
+
+fcvtms s0, d1
+// CHECK-INST: fcvtms s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x74,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e740020 <unknown>
+
+fcvtms s1, h2
+// CHECK-INST: fcvtms s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xf4,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1ef40041 <unknown>
+
+fcvtms d3, h4
+// CHECK-INST: fcvtms d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xf4,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9ef40083 <unknown>
+
+fcvtms d0, s5
+// CHECK-INST: fcvtms d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x34,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3400a0 <unknown>
+
+fcvtmu s0, d1
+// CHECK-INST: fcvtmu s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x75,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e750020 <unknown>
+
+fcvtmu s1, h2
+// CHECK-INST: fcvtmu s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xf5,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1ef50041 <unknown>
+
+fcvtmu d3, h4
+// CHECK-INST: fcvtmu d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xf5,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9ef50083 <unknown>
+
+fcvtmu d0, s5
+// CHECK-INST: fcvtmu d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x35,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3500a0 <unknown>
+
+fcvtns s0, d1
+// CHECK-INST: fcvtns s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x6a,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e6a0020 <unknown>
+
+fcvtns s1, h2
+// CHECK-INST: fcvtns s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xea,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1eea0041 <unknown>
+
+fcvtns d3, h4
+// CHECK-INST: fcvtns d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xea,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9eea0083 <unknown>
+
+fcvtns d0, s5
+// CHECK-INST: fcvtns d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x2a,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e2a00a0 <unknown>
+
+fcvtnu s0, d1
+// CHECK-INST: fcvtnu s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x6b,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e6b0020 <unknown>
+
+fcvtnu s1, h2
+// CHECK-INST: fcvtnu s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xeb,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1eeb0041 <unknown>
+
+fcvtnu d3, h4
+// CHECK-INST: fcvtnu d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xeb,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9eeb0083 <unknown>
+
+fcvtnu d0, s5
+// CHECK-INST: fcvtnu d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x2b,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e2b00a0 <unknown>
+
+fcvtps s0, d1
+// CHECK-INST: fcvtps s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x72,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e720020 <unknown>
+
+fcvtps s1, h2
+// CHECK-INST: fcvtps s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xf2,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1ef20041 <unknown>
+
+fcvtps d3, h4
+// CHECK-INST: fcvtps d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xf2,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9ef20083 <unknown>
+
+fcvtps d0, s5
+// CHECK-INST: fcvtps d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x32,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3200a0 <unknown>
+
+fcvtpu s0, d1
+// CHECK-INST: fcvtpu s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x73,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e730020 <unknown>
+
+fcvtpu s1, h2
+// CHECK-INST: fcvtpu s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xf3,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1ef30041 <unknown>
+
+fcvtpu d3, h4
+// CHECK-INST: fcvtpu d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xf3,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9ef30083 <unknown>
+
+fcvtpu d0, s5
+// CHECK-INST: fcvtpu d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x33,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3300a0 <unknown>
+
+fcvtzs s0, d1
+// CHECK-INST: fcvtzs s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x76,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e760020 <unknown>
+
+fcvtzs s1, h2
+// CHECK-INST: fcvtzs s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xf6,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1ef60041 <unknown>
+
+fcvtzs d3, h4
+// CHECK-INST: fcvtzs d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xf6,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9ef60083 <unknown>
+
+fcvtzs d0, s5
+// CHECK-INST: fcvtzs d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x36,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3600a0 <unknown>
+
+fcvtzu s0, d1
+// CHECK-INST: fcvtzu s0, d1
+// CHECK-ENCODING: [0x20,0x00,0x77,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1e770020 <unknown>
+
+fcvtzu s1, h2
+// CHECK-INST: fcvtzu s1, h2
+// CHECK-ENCODING: [0x41,0x00,0xf7,0x1e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 1ef70041 <unknown>
+
+fcvtzu d3, h4
+// CHECK-INST: fcvtzu d3, h4
+// CHECK-ENCODING: [0x83,0x00,0xf7,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9ef70083 <unknown>
+
+fcvtzu d0, s5
+// CHECK-INST: fcvtzu d0, s5
+// CHECK-ENCODING: [0xa0,0x00,0x37,0x9e]
+// CHECK-ERROR: instruction requires: fprcvt
+// CHECK-UNKNOWN: 9e3700a0 <unknown>
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/directive-arch-negative.s b/llvm/test/MC/AArch64/directive-arch-negative.s
index d037387a2cb77a..1d959ddea98f14 100644
--- a/llvm/test/MC/AArch64/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch-negative.s
@@ -56,3 +56,21 @@
# CHECK: error: instruction requires: lse
# CHECK-NEXT: casa w5, w7, [x20]
+
+ .arch armv9.6.-a+nofprcvt
+ scvtf d1, s2
+
+# CHECK: error: instruction requires: fprcvt
+# CHECK-NEXT: scvtf d1, s2
+
+ .arch armv9.6.-a+nof8f16mm
+ fmmla v0.8h, v1.16b, v2.16b
+
+# CHECK: error: instruction requires: f8f16mm
+# CHECK-NEXT: fmmla v0.8h, v1.16b, v2.16b
+
+ .arch armv9.6.-a+nof8f32mm
+ fmmla v0.4s, v1.16b, v2.16b
+
+# CHECK: error: instruction requires: f8f32mm
+# CHECK-NEXT: fmmla v0.4s, v1.16b, v2.16b
diff --git a/llvm/test/MC/AArch64/directive-arch.s b/llvm/test/MC/AArch64/directive-arch.s
index 32840b4cd14222..99f7dcb6ec5066 100644
--- a/llvm/test/MC/AArch64/directive-arch.s
+++ b/llvm/test/MC/AArch64/directive-arch.s
@@ -21,3 +21,15 @@
mrs x0, rndrrs
# CHECK: mrs x0, RNDR
# CHECK: mrs x0, RNDRRS
+
+ .arch armv9-a+fprcvt
+ scvtf h1, s2
+# CHECK: scvtf h1, s2
+
+ .arch armv9-a+f8f16mm
+ fmmla v0.8h, v1.16b, v2.16b
+# CHECK: fmmla v0.8h, v1.16b, v2.16b
+
+ .arch armv9-a+f8f32mm
+ fmmla v0.4s, v1.16b, v2.16b
+# CHECK: fmmla v0.4s, v1.16b, v2.16b
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 1843af56555461..ce39ff51ce5c73 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -1,6 +1,6 @@
// RUN: not llvm-mc -triple aarch64 \
// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
-// RUN: -mattr=+rcpc3,+lse128,+d128,+the,+rasv2,+ite,+cssc,+specres2,+gcs \
+// RUN: -mattr=+rcpc3,+lse128,+d128,+the,+rasv2,+ite,+cssc,+specres2,+gcs, \
// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension axp64
@@ -229,3 +229,21 @@ gcspushm x0
gcspushm x0
// CHECK: [[@LINE-1]]:1: error: instruction requires: gcs
// CHECK-NEXT: gcspushm x0
+
+.arch_extension fprcvt
+.arch_extension nofprcvt
+fcvtmu s0, d1
+// CHECK: [[@LINE-1]]:1: error: instruction requires: fprcvt
+// CHECK-NEXT: fcvtmu s0, d1
+
+.arch_extension f8f16mm
+.arch_extension nof8f16mm
+fmmla v2.8h, v1.16b, v0.16b
+// CHECK: [[@LINE-1]]:1: error: instruction requires: f8f16mm
+// CHECK-NEXT: fmmla v2.8h, v1.16b, v0.16b
+
+.arch_extension f8f32mm
+.arch_extension nof8f32mm
+fmmla v2.4s, v1.16b, v0.16b
+// CHECK: [[@LINE-1]]:1: error: instruction requires: f8f32mm
+// CHECK-NEXT: fmmla v2.4s, v1.16b, v0.16b
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s
index 8a0e1ac471cea7..b8e8696c7abbf1 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -189,3 +189,15 @@ msr SSBS, #1
.arch_extension tme
tstart x0
// CHECK: tstart x0
+
+.arch_extension fprcvt
+fcvtns s0, d1
+// CHECK: fcvtns s0, d1
+
+.arch_extension f8f16mm
+fmmla v1.8h, v2.16b, v3.16b
+// CHECK: fmmla v1.8h, v2.16b, v3.16b
+
+.arch_extension f8f32mm
+fmmla v1.4s, v2.16b, v3.16b
+// CHECK: fmmla v1.4s, v2.16b, v3.16b
diff --git a/llvm/test/MC/AArch64/directive-cpu.s b/llvm/test/MC/AArch64/directive-cpu.s
index e3d7b1cd75e550..1a0a0bd0c5132c 100644
--- a/llvm/test/MC/AArch64/directive-cpu.s
+++ b/llvm/test/MC/AArch64/directive-cpu.s
@@ -39,3 +39,15 @@ sha512h q0, q1, v2.2d
.cpu generic+sm4
sm4e v2.4s, v15.4s
// CHECK: sm4e v2.4s, v15.4s
+
+.cpu generic+fprcvt
+scvtf d1, s2
+// CHECK: scvtf d1, s2
+
+.cpu generic+f8f16mm
+fmmla v0.8h, v1.16b, v2.16b
+// CHECK: fmmla v0.8h, v1.16b, v2.16b
+
+.cpu generic+f8f32mm
+fmmla v0.4s, v1.16b, v2.16b
+// CHECK: fmmla v0.4s, v1.16b, v2.16b
diff --git a/llvm/test/MC/AArch64/neon-diagnostics.s b/llvm/test/MC/AArch64/neon-diagnostics.s
index 9a0445131ddf7c..6863a89bbe189e 100644
--- a/llvm/test/MC/AArch64/neon-diagnostics.s
+++ b/llvm/test/MC/AArch64/neon-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon < %s 2> %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon,+fprcvt < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
//------------------------------------------------------------------------------
@@ -5176,6 +5176,32 @@
// CHECK-ERROR: ucvtf d21, s14, #64
// CHECK-ERROR: ^
+//----------------------------------------------------------------------
+// Scalar Signed Integer Convert To Floating-Point
+//---------------------------------------------------------------------
+
+ scvtf d0, h0
+ scvtf s0, h0
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: scvtf d0, h0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: scvtf s0, h0
+// CHECK-ERROR: ^
+
+//----------------------------------------------------------------------
+// Scalar Unsigned Integer Convert To Floating-Point
+//---------------------------------------------------------------------
+
+ ucvtf d0, h0
+ ucvtf s0, h0
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: ucvtf d0, h0
+// CHECK-ERROR: ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: ucvtf s0, h0
+// CHECK-ERROR: ^
+
//------------------------------------------------------------------------------
// Element reverse
//------------------------------------------------------------------------------
@@ -6943,14 +6969,14 @@
// With Ties To Away
//----------------------------------------------------------------------
- fcvtas s0, d0
- fcvtas d0, s0
+ fcvtas h0, d0
+ fcvtas h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtas s0, d0
+// CHECK-ERROR: fcvtas h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtas d0, s0
+// CHECK-ERROR: fcvtas h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -6958,14 +6984,14 @@
// Nearest With Ties To Away
//----------------------------------------------------------------------
- fcvtau s0, d0
- fcvtau d0, s0
+ fcvtau h0, d0
+ fcvtau h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtau s0, d0
+// CHECK-ERROR: fcvtau h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtau d0, s0
+// CHECK-ERROR: fcvtau h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -6973,14 +6999,14 @@
// Minus Infinity
//----------------------------------------------------------------------
- fcvtms s0, d0
- fcvtms d0, s0
+ fcvtms h0, d0
+ fcvtms h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtms s0, d0
+// CHECK-ERROR: fcvtms h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtms d0, s0
+// CHECK-ERROR: fcvtms h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -6988,14 +7014,14 @@
// Minus Infinity
//----------------------------------------------------------------------
- fcvtmu s0, d0
- fcvtmu d0, s0
+ fcvtmu h0, d0
+ fcvtmu h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtmu s0, d0
+// CHECK-ERROR: fcvtmu h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtmu d0, s0
+// CHECK-ERROR: fcvtmu h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -7003,14 +7029,14 @@
// With Ties To Even
//----------------------------------------------------------------------
- fcvtns s0, d0
- fcvtns d0, s0
+ fcvtns h0, d0
+ fcvtns h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtns s0, d0
+// CHECK-ERROR: fcvtns h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtns d0, s0
+// CHECK-ERROR: fcvtns h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -7018,14 +7044,14 @@
// Nearest With Ties To Even
//----------------------------------------------------------------------
- fcvtnu s0, d0
- fcvtnu d0, s0
+ fcvtnu h0, d0
+ fcvtnu h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtnu s0, d0
+// CHECK-ERROR: fcvtnu h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtnu d0, s0
+// CHECK-ERROR: fcvtnu h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -7033,14 +7059,14 @@
// Positive Infinity
//----------------------------------------------------------------------
- fcvtps s0, d0
- fcvtps d0, s0
+ fcvtps h0, d0
+ fcvtps h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtps s0, d0
+// CHECK-ERROR: fcvtps h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtps d0, s0
+// CHECK-ERROR: fcvtps h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -7048,28 +7074,28 @@
// Positive Infinity
//----------------------------------------------------------------------
- fcvtpu s0, d0
- fcvtpu d0, s0
+ fcvtpu h0, d0
+ fcvtpu h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtpu s0, d0
+// CHECK-ERROR: fcvtpu h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtpu d0, s0
+// CHECK-ERROR: fcvtpu h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero
//----------------------------------------------------------------------
- fcvtzs s0, d0
- fcvtzs d0, s0
+ fcvtzs h0, d0
+ fcvtzs h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtzs s0, d0
+// CHECK-ERROR: fcvtzs h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtzs d0, s0
+// CHECK-ERROR: fcvtzs h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
@@ -7077,14 +7103,14 @@
// Zero
//----------------------------------------------------------------------
- fcvtzu s0, d0
- fcvtzu d0, s0
+ fcvtzu h0, d0
+ fcvtzu h0, s0
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtzu s0, d0
+// CHECK-ERROR: fcvtzu h0, d0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR: fcvtzu d0, s0
+// CHECK-ERROR: fcvtzu h0, s0
// CHECK-ERROR: ^
//----------------------------------------------------------------------
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