[llvm] [AARCH64] Add assembly/disassembly for FMMLA instructions (PR #113313)

[via llvm-commits]

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@@ -29,3 +29,21 @@ rax1 z0.d, z0.d, z0.d
 bgrp z21.s, z10.s, z21.s
 // CHECK: error: instruction requires: sve2-bitperm
 // CHECK-NEXT: bgrp z21.s, z10.s, z21.s
+
+.arch armv9-a+sve2+f8f16mm
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Lukacma wrote:

Done

https://github.com/llvm/llvm-project/pull/113313