[llvm] [RISCV] Separate HW/SW shadow stack on RISC-V (PR #112478)
Jesse Huang via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 22 23:38:48 PDT 2024
================
@@ -73,7 +77,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
return;
const RISCVInstrInfo *TII = STI.getInstrInfo();
- if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
+ if (HasHWShadowStack) {
BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
----------------
jaidTw wrote:
I guess Kito is too busy, so I just choose to loosen the requirement in tablegen to Zimop
https://github.com/llvm/llvm-project/pull/112478
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