[llvm] [TableGen] Added submulticlass typechecking to template arg values. (PR #112904)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 22 15:24:18 PDT 2024
https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/112904
>From 24da282e3ccf5c84c69418407f6c996938697a7a Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Fri, 18 Oct 2024 02:15:49 -0400
Subject: [PATCH 1/7] [TableGen] Added submulticlass typechecking to template
arg values.
Some typechecking was missing when parsing a submulticlass reference.
This adds it in and fixes any mistyped codes in .td files.
---
llvm/lib/TableGen/TGParser.cpp | 6 ++++++
llvm/lib/Target/AMDGPU/VOPInstructions.td | 2 +-
llvm/lib/Target/ARM/ARMInstrMVE.td | 8 ++++----
llvm/test/TableGen/submulticlass-typecheck.td | 12 ++++++++++++
4 files changed, 23 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/TableGen/submulticlass-typecheck.td
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index f315557f38aadd..cffd40115168ef 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -818,6 +818,12 @@ ParseSubMultiClassReference(MultiClass *CurMC) {
return Result;
}
+ if (CheckTemplateArgValues(Result.TemplateArgs, Result.RefRange.Start,
+ &Result.MC->Rec)) {
+ Result.MC = nullptr; // Error checking value list.
+ return Result;
+ }
+
Result.RefRange.End = Lex.getLoc();
return Result;
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index aab5dc7465d938..cd8777ac114bf8 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -37,7 +37,7 @@ defvar VOPDX_Max_Index = 12;
class VOPD_Component<bits<5> OpIn, string vOPDName> {
Instruction BaseVOP = !cast<Instruction>(NAME);
- string VOPDName = "v_dual_" # !substr(vOPDName, 2);
+ string VOPDName = "v_dual_" # !if(!le(!size(vOPDName), 2), "", !substr(vOPDName, 2));
bits<5> VOPDOp = OpIn;
bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index);
}
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 04d5d00eef10e6..c3c4963a5da288 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2199,7 +2199,7 @@ def subnsw : PatFrag<(ops node:$lhs, node:$rhs),
}]>;
multiclass MVE_VRHADD_m<MVEVectorVTInfo VTI, SDNode Op,
- SDPatternOperator unpred_op, Intrinsic PredInt> {
+ DefaultAttrsIntrinsic unpred_op, Intrinsic PredInt> {
def "" : MVE_VRHADD_Base<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
@@ -2303,7 +2303,7 @@ class MVE_VHSUB_<string suffix, bit U, bits<2> size,
: MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
multiclass MVE_VHADD_m<MVEVectorVTInfo VTI, SDNode Op,
- SDPatternOperator unpred_op, Intrinsic PredInt, PatFrag add_op,
+ DefaultAttrsIntrinsic unpred_op, Intrinsic PredInt, PatFrag add_op,
SDNode shift_op> {
def "" : MVE_VHADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
@@ -2335,7 +2335,7 @@ defm MVE_VHADDu16 : MVE_VHADD<MVE_v8u16, avgflooru, addnuw, ARMvshruImm>;
defm MVE_VHADDu32 : MVE_VHADD<MVE_v4u32, avgflooru, addnuw, ARMvshruImm>;
multiclass MVE_VHSUB_m<MVEVectorVTInfo VTI,
- SDPatternOperator unpred_op, Intrinsic pred_int, PatFrag sub_op,
+ DefaultAttrsIntrinsic unpred_op, Intrinsic pred_int, PatFrag sub_op,
SDNode shift_op> {
def "" : MVE_VHSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
@@ -4794,7 +4794,7 @@ class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size, bit round,
let validForTailPredication = 1;
}
-multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDPatternOperator unpred_op,
+multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, DefaultAttrsIntrinsic unpred_op,
Intrinsic PredInt, bit round> {
def "" : MVE_VxMULH<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, round>;
defvar Inst = !cast<Instruction>(NAME);
diff --git a/llvm/test/TableGen/submulticlass-typecheck.td b/llvm/test/TableGen/submulticlass-typecheck.td
new file mode 100644
index 00000000000000..2a1f7ab094f881
--- /dev/null
+++ b/llvm/test/TableGen/submulticlass-typecheck.td
@@ -0,0 +1,12 @@
+// RUN: not llvm-tblgen %s 2>&1 | FileCheck %s
+// XFAIL: vg_leak
+// CHECK: {{.*}}: error: Value specified for template argument 'B::op' is of type bits<4>; expected type bits<8>: C::op
+// CHECK-NEXT: multiclass C<bits<4> op> : B<op>;
+class A<bits<8> op> {
+ bits<8> f = op;
+}
+multiclass B<bits<8> op> {
+ def : A<op>;
+}
+multiclass C<bits<4> op> : B<op>;
+defm D : C<0>;
>From 8872da7826baa593a2afccdffed5199378a893dc Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Sun, 20 Oct 2024 12:48:33 -0400
Subject: [PATCH 2/7] Give _fake16 record a vOPDName so that it now has a
suffix in VOPDName.
The record now looks like:
def V_CNDMASK_B16_e32 {
...
Instruction BaseVOP = V_CNDMASK_B16_e32;
string VOPDName = "v_dual_";
bits<5> VOPDOp = { 1, 1, 1, 1, 1 };
bit CanBeVOPDX = 0;
-->
Instruction BaseVOP = V_CNDMASK_B16_e32;
string VOPDName = "v_dual_cndmask_b16";
bits<5> VOPDOp = { 1, 1, 1, 1, 1 };
bit CanBeVOPDX = 0;
}
Whereas before, these fields were omitted entirely.
---
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 +-
llvm/lib/Target/AMDGPU/VOPInstructions.td | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index fbde3bb7d14111..580ab047027d94 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -319,7 +319,7 @@ multiclass
multiclass
VOP2eInst<string opName, VOPProfile P, SDPatternOperator node = null_frag,
string revOp = opName, bit useSGPRInput = !eq(P.NumSrcArgs, 3)>
- : VOP2eInst_Base<opName, P, 0, "", node, revOp, useSGPRInput>;
+ : VOP2eInst_Base<opName, P, -1, "v_cndmask_b16", node, revOp, useSGPRInput>;
multiclass
VOP2eInst_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName,
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index cd8777ac114bf8..aab5dc7465d938 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -37,7 +37,7 @@ defvar VOPDX_Max_Index = 12;
class VOPD_Component<bits<5> OpIn, string vOPDName> {
Instruction BaseVOP = !cast<Instruction>(NAME);
- string VOPDName = "v_dual_" # !if(!le(!size(vOPDName), 2), "", !substr(vOPDName, 2));
+ string VOPDName = "v_dual_" # !substr(vOPDName, 2);
bits<5> VOPDOp = OpIn;
bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index);
}
>From 9fcd0c453eb44be15876f0d134376125318cd849 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Sun, 20 Oct 2024 13:04:19 -0400
Subject: [PATCH 3/7] Add line number to assertion
---
llvm/test/TableGen/submulticlass-typecheck.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/TableGen/submulticlass-typecheck.td b/llvm/test/TableGen/submulticlass-typecheck.td
index 2a1f7ab094f881..b128d93e7b2388 100644
--- a/llvm/test/TableGen/submulticlass-typecheck.td
+++ b/llvm/test/TableGen/submulticlass-typecheck.td
@@ -1,6 +1,6 @@
// RUN: not llvm-tblgen %s 2>&1 | FileCheck %s
// XFAIL: vg_leak
-// CHECK: {{.*}}: error: Value specified for template argument 'B::op' is of type bits<4>; expected type bits<8>: C::op
+// CHECK: {{.*}}:11:28: error: Value specified for template argument 'B::op' is of type bits<4>; expected type bits<8>: C::op
// CHECK-NEXT: multiclass C<bits<4> op> : B<op>;
class A<bits<8> op> {
bits<8> f = op;
>From b0a59fba7b90de81898cdcff79c68ac9e266bcff Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Mon, 21 Oct 2024 12:10:22 -0400
Subject: [PATCH 4/7] Change vOPDName to be prefix that is ignored by !substr
in fake record.
Now the record has this field as before, and the fake part is included
in the record:
string VOPDName = "v_dual_";
---
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 +-
llvm/lib/Target/AMDGPU/VOPInstructions.td | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 580ab047027d94..b545a58e2b12f2 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -319,7 +319,7 @@ multiclass
multiclass
VOP2eInst<string opName, VOPProfile P, SDPatternOperator node = null_frag,
string revOp = opName, bit useSGPRInput = !eq(P.NumSrcArgs, 3)>
- : VOP2eInst_Base<opName, P, -1, "v_cndmask_b16", node, revOp, useSGPRInput>;
+ : VOP2eInst_Base<opName, P, -1, "v_", node, revOp, useSGPRInput>;
multiclass
VOP2eInst_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName,
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index aab5dc7465d938..d19df4a3f16e62 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -1931,4 +1931,4 @@ def VOPTrue16Table : GenericTable {
let PrimaryKey = ["Opcode"];
let PrimaryKeyName = "getTrue16OpcodeHelper";
-}
+}
\ No newline at end of file
>From d3e9c8812bc719bf13e2ce77ec1f55aa353e4c97 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Mon, 21 Oct 2024 20:15:27 -0400
Subject: [PATCH 5/7] Add let !eq in submulticlass test.
---
llvm/test/TableGen/submulticlass-leteq.td | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 llvm/test/TableGen/submulticlass-leteq.td
diff --git a/llvm/test/TableGen/submulticlass-leteq.td b/llvm/test/TableGen/submulticlass-leteq.td
new file mode 100644
index 00000000000000..eeaa523d870ec7
--- /dev/null
+++ b/llvm/test/TableGen/submulticlass-leteq.td
@@ -0,0 +1,21 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+// CHECK: def X0 { // C
+// CHECK-NEXT: bit x = 1;
+// CHECK-NEXT: }
+// CHECK-NEXT: def X1 { // C
+// CHECK-NEXT: bit x = 0;
+// CHECK-NEXT: }
+class C {
+ bit x;
+}
+multiclass M0<bits<8> Val> {
+ let x = !eq(Val, !cast<bits<8>>(-1)) in def NAME : C;
+}
+multiclass M1<bits<8> Val> {
+ let x = !eq(Val, -1) in def NAME : C;
+}
+multiclass M2_0 : M0<-1>;
+multiclass M2_1 : M1<-1>;
+defm X0 : M2_0;
+defm X1 : M2_1;
>From 4a200343fce3a2fe2e677ac0b336dfaf80372766 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Tue, 22 Oct 2024 08:04:28 -0400
Subject: [PATCH 6/7] Remove prefix in fake record and rebase to b3acb25.
---
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 +-
llvm/lib/Target/AMDGPU/VOPInstructions.td | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index b545a58e2b12f2..fbde3bb7d14111 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -319,7 +319,7 @@ multiclass
multiclass
VOP2eInst<string opName, VOPProfile P, SDPatternOperator node = null_frag,
string revOp = opName, bit useSGPRInput = !eq(P.NumSrcArgs, 3)>
- : VOP2eInst_Base<opName, P, -1, "v_", node, revOp, useSGPRInput>;
+ : VOP2eInst_Base<opName, P, 0, "", node, revOp, useSGPRInput>;
multiclass
VOP2eInst_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName,
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index d19df4a3f16e62..aab5dc7465d938 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -1931,4 +1931,4 @@ def VOPTrue16Table : GenericTable {
let PrimaryKey = ["Opcode"];
let PrimaryKeyName = "getTrue16OpcodeHelper";
-}
\ No newline at end of file
+}
>From ae9da089c65480588b2845a6f31aa8fe4c6e9d41 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Tue, 22 Oct 2024 14:48:56 -0400
Subject: [PATCH 7/7] Use the more derived type
---
llvm/lib/Target/ARM/ARMInstrMVE.td | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index c3c4963a5da288..04d5d00eef10e6 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2199,7 +2199,7 @@ def subnsw : PatFrag<(ops node:$lhs, node:$rhs),
}]>;
multiclass MVE_VRHADD_m<MVEVectorVTInfo VTI, SDNode Op,
- DefaultAttrsIntrinsic unpred_op, Intrinsic PredInt> {
+ SDPatternOperator unpred_op, Intrinsic PredInt> {
def "" : MVE_VRHADD_Base<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
@@ -2303,7 +2303,7 @@ class MVE_VHSUB_<string suffix, bit U, bits<2> size,
: MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
multiclass MVE_VHADD_m<MVEVectorVTInfo VTI, SDNode Op,
- DefaultAttrsIntrinsic unpred_op, Intrinsic PredInt, PatFrag add_op,
+ SDPatternOperator unpred_op, Intrinsic PredInt, PatFrag add_op,
SDNode shift_op> {
def "" : MVE_VHADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
@@ -2335,7 +2335,7 @@ defm MVE_VHADDu16 : MVE_VHADD<MVE_v8u16, avgflooru, addnuw, ARMvshruImm>;
defm MVE_VHADDu32 : MVE_VHADD<MVE_v4u32, avgflooru, addnuw, ARMvshruImm>;
multiclass MVE_VHSUB_m<MVEVectorVTInfo VTI,
- DefaultAttrsIntrinsic unpred_op, Intrinsic pred_int, PatFrag sub_op,
+ SDPatternOperator unpred_op, Intrinsic pred_int, PatFrag sub_op,
SDNode shift_op> {
def "" : MVE_VHSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
@@ -4794,7 +4794,7 @@ class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size, bit round,
let validForTailPredication = 1;
}
-multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, DefaultAttrsIntrinsic unpred_op,
+multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDPatternOperator unpred_op,
Intrinsic PredInt, bit round> {
def "" : MVE_VxMULH<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, round>;
defvar Inst = !cast<Instruction>(NAME);
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