[llvm] [llvm][TableGen] Allow physical registers in patterns for GlobalISel emitter (PR #113127)

[via llvm-commits]

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@@ -3,10 +3,34 @@
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
-// CHECK: Skipped pattern: Pattern defines a physical register
 let Uses = [B0], Defs = [B0] in
 def tst1 : I<(outs), (ins), [(set B0, (add B0, 1))]>;
 
-// CHECK: Skipped pattern: Src pattern result has 1 def(s) without the HasNoUse predicate set to true but Dst MI has no def
+// CHECK: Skipped pattern: unhandled discarded def
 let Uses = [B0] in
 def tst2 : I<(outs), (ins), [(set B0, (add B0, 1))]>;
+
+// test courtesy @s-barannikov
+def SDTBinOpWithFlagsOut : SDTypeProfile<2, 2, [
+  SDTCisInt<0>,       // result
+  SDTCisVT<1, i32>,   // out flags
+  SDTCisSameAs<2, 0>, // lhs
+  SDTCisSameAs<3, 0>  // rhs
+]>;
+
+def my_sub : SDNode<"MyTargetISD::SUB", SDTBinOpWithFlagsOut>;
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JL2210 wrote:

I'm not sure what you mean by that. I haven't really used these since they don't get imported. Can you give an example?

https://github.com/llvm/llvm-project/pull/113127