[llvm] 78e026f - [RISCV][NFC] Document F64 ISD Nodes

[Sam Elliott via llvm-commits]

Author: Sam Elliott
Date: 2024-10-22T11:45:12-07:00
New Revision: 78e026f845fb4d924673a9d534cc36cf7b55473c

URL: https://github.com/llvm/llvm-project/commit/78e026f845fb4d924673a9d534cc36cf7b55473c
DIFF: https://github.com/llvm/llvm-project/commit/78e026f845fb4d924673a9d534cc36cf7b55473c.diff

LOG: [RISCV][NFC] Document F64 ISD Nodes

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 62d6b37d9b9196..4e116cd8b5b87a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -43,7 +43,17 @@ enum NodeType : unsigned {
   /// integer or floating point.
   SELECT_CC,
   BR_CC,
+
+  /// Turns a pair of `i32`s into an `f64`. Needed for rv32d/ilp32.
+  /// - Output: `f64`.
+  /// - Input 0: low-order bits (31-0) (as `i32`), for even register.
+  /// - Input 1: high-order bits (63-32) (as `i32`), for odd register.
   BuildPairF64,
+
+  /// Turns a `f64` into a pair of `i32`s. Needed for rv32d/ilp32.
+  /// - Output 0: low-order bits (31-0) (as `i32`), from even register.
+  /// - Output 1: high-order bits (63-32) (as `i32`), from odd register.
+  /// - Input 0: `f64`.
   SplitF64,
 
   // Add the Lo 12 bits from an address. Selected to ADDI.