[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

[Sam Elliott via llvm-commits]

lenary wrote:

I gave up on using `splitValueIntoRegisterParts` and `joinRegisterPartsIntoValue`, and instead added a custom legalisation of `BITCAST` with the 2*xlen type, which matches what we do for `BuildPairF64` and `SplitF64`. This ended up being much more "symmetrical", which was nice.

I'm still doing Selection entirely in C++, as I think we'd need to go to C++ anyway to emit the right REG_SEQUENCE and EXTRACT_SUBREG.

I've not implemented anything in `RISCVTargetLowering::PerformDAGCombine` for `BuildPairGPR` and `SplitPairGPR` - though I see there's something in there for `SplitF64`, and not all of it is FP-related. I don't know how much of a difference these combines will make when the generated instructions are not as expensive as the stack slot that `BuildPairF64`/`SplitF64` sometimes needs.

Instead of looking at combines, I'm going to try to get the tests to work with GlobalISel. 

https://github.com/llvm/llvm-project/pull/112983